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Function intel_dp_setup_hdr_metadata_infoframe_sdp handles Infoframe SDP
header and data block setup for HDR Static Metadata. It enables writing of
HDR metadata infoframe SDP to panel. Support for HDR video was introduced
in DisplayPort 1.4. It implements the CTA-861-G standard for transport of
static HDR metadata. The HDR Metadata will be provided by userspace
compositors, based on blending policies and passed to the driver through
a blob property.
Because each of GEN11 and prior GEN11 have different register size for
HDR Metadata Infoframe SDP packet, it adds and uses different register
size.
Setup Infoframe SDP header and data block in function
intel_dp_setup_hdr_metadata_infoframe_sdp for HDR Static Metadata as per
dp 1.4 spec and CTA-861-F spec.
As per DP 1.4 spec, 2.2.2.5 SDP Formats. It enables Dynamic Range and
Mastering Infoframe for HDR content, which is defined in CTA-861-F spec.
According to DP 1.4 spec and CEA-861-F spec Table 5, in order to transmit
static HDR metadata, we have to use Non-audio INFOFRAME SDP v1.3.
+--------------------------------+-------------------------------+
| [ Packet Type Value ] | [ Packet Type ] |
+--------------------------------+-------------------------------+
| 80h + Non-audio INFOFRAME Type | CEA-861-F Non-audio INFOFRAME |
+--------------------------------+-------------------------------+
| [Transmission Timing] |
+----------------------------------------------------------------+
| As per CEA-861-F for INFOFRAME, including CEA-861.3 within |
| which Dynamic Range and Mastering INFOFRAME are defined |
+----------------------------------------------------------------+
v2: Add a missed blank line after function declaration.
v3: Remove not handled return values from
intel_dp_setup_hdr_metadata_infoframe_sdp(). [Uma]
v9: Addressed review comments from Ville.
- Add BUILD_BUG_ON to check a changing of struct dp_sdp size.
- Change a passed size toward write_infoframe() for DP infoframe sdp
packet for HDR static metadata.
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190919195311.13972-8-gwan-gyeong.mun@intel.com
129 lines
5.0 KiB
C
129 lines
5.0 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2019 Intel Corporation
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*/
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#ifndef __INTEL_DP_H__
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#define __INTEL_DP_H__
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#include <linux/types.h>
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#include <drm/i915_drm.h>
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#include "i915_reg.h"
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enum pipe;
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enum port;
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struct drm_connector_state;
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struct drm_encoder;
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struct drm_i915_private;
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struct drm_modeset_acquire_ctx;
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struct intel_connector;
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struct intel_crtc_state;
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struct intel_digital_port;
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struct intel_dp;
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struct intel_encoder;
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struct link_config_limits {
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int min_clock, max_clock;
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int min_lane_count, max_lane_count;
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int min_bpp, max_bpp;
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};
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void intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
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struct intel_crtc_state *pipe_config,
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struct link_config_limits *limits);
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bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
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const struct drm_connector_state *conn_state);
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int intel_dp_min_bpp(const struct intel_crtc_state *crtc_state);
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bool intel_dp_port_enabled(struct drm_i915_private *dev_priv,
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i915_reg_t dp_reg, enum port port,
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enum pipe *pipe);
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bool intel_dp_init(struct drm_i915_private *dev_priv, i915_reg_t output_reg,
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enum port port);
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bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
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struct intel_connector *intel_connector);
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void intel_dp_set_link_params(struct intel_dp *intel_dp,
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int link_rate, u8 lane_count,
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bool link_mst);
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int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
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int link_rate, u8 lane_count);
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int intel_dp_retrain_link(struct intel_encoder *encoder,
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struct drm_modeset_acquire_ctx *ctx);
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void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
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void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
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const struct intel_crtc_state *crtc_state,
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bool enable);
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void intel_dp_encoder_reset(struct drm_encoder *encoder);
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void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
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void intel_dp_encoder_flush_work(struct drm_encoder *encoder);
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int intel_dp_compute_config(struct intel_encoder *encoder,
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struct intel_crtc_state *pipe_config,
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struct drm_connector_state *conn_state);
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bool intel_dp_is_edp(struct intel_dp *intel_dp);
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bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
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enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
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bool long_hpd);
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void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
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const struct drm_connector_state *conn_state);
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void intel_edp_backlight_off(const struct drm_connector_state *conn_state);
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void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
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void intel_edp_panel_on(struct intel_dp *intel_dp);
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void intel_edp_panel_off(struct intel_dp *intel_dp);
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void intel_dp_mst_suspend(struct drm_i915_private *dev_priv);
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void intel_dp_mst_resume(struct drm_i915_private *dev_priv);
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int intel_dp_max_link_rate(struct intel_dp *intel_dp);
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int intel_dp_max_lane_count(struct intel_dp *intel_dp);
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int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
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void intel_power_sequencer_reset(struct drm_i915_private *dev_priv);
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u32 intel_dp_pack_aux(const u8 *src, int src_bytes);
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void intel_edp_drrs_enable(struct intel_dp *intel_dp,
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const struct intel_crtc_state *crtc_state);
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void intel_edp_drrs_disable(struct intel_dp *intel_dp,
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const struct intel_crtc_state *crtc_state);
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void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
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unsigned int frontbuffer_bits);
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void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
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unsigned int frontbuffer_bits);
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void
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intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
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u8 dp_train_pat);
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void
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intel_dp_set_signal_levels(struct intel_dp *intel_dp);
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void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
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u8
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intel_dp_voltage_max(struct intel_dp *intel_dp);
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u8
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intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, u8 voltage_swing);
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void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
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u8 *link_bw, u8 *rate_select);
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bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
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bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp);
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bool
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intel_dp_get_link_status(struct intel_dp *intel_dp, u8 *link_status);
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bool intel_dp_read_dpcd(struct intel_dp *intel_dp);
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bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp);
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int intel_dp_link_required(int pixel_clock, int bpp);
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int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
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bool intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
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const struct drm_connector_state *conn_state);
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void intel_dp_vsc_enable(struct intel_dp *intel_dp,
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const struct intel_crtc_state *crtc_state,
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const struct drm_connector_state *conn_state);
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void intel_dp_hdr_metadata_enable(struct intel_dp *intel_dp,
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const struct intel_crtc_state *crtc_state,
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const struct drm_connector_state *conn_state);
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bool intel_digital_port_connected(struct intel_encoder *encoder);
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static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
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{
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return ~((1 << lane_count) - 1) & 0xf;
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}
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u32 intel_dp_mode_to_fec_clock(u32 mode_clock);
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#endif /* __INTEL_DP_H__ */
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