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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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45bce1719c
This patch adds support for using the PTP register range, and adds a description of its registers. This bank is used when configuring PTP. Signed-off-by: Antoine Tenart <antoine.tenart@bootlin.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
42 lines
941 B
C
42 lines
941 B
C
/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
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/*
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* Microsemi Ocelot Switch driver
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*
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* License: Dual MIT/GPL
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* Copyright (c) 2017 Microsemi Corporation
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*/
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#ifndef _MSCC_OCELOT_PTP_H_
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#define _MSCC_OCELOT_PTP_H_
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#define PTP_PIN_CFG_RSZ 0x20
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#define PTP_PIN_TOD_SEC_MSB_RSZ PTP_PIN_CFG_RSZ
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#define PTP_PIN_TOD_SEC_LSB_RSZ PTP_PIN_CFG_RSZ
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#define PTP_PIN_TOD_NSEC_RSZ PTP_PIN_CFG_RSZ
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#define PTP_PIN_CFG_DOM BIT(0)
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#define PTP_PIN_CFG_SYNC BIT(2)
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#define PTP_PIN_CFG_ACTION(x) ((x) << 3)
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#define PTP_PIN_CFG_ACTION_MASK PTP_PIN_CFG_ACTION(0x7)
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enum {
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PTP_PIN_ACTION_IDLE = 0,
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PTP_PIN_ACTION_LOAD,
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PTP_PIN_ACTION_SAVE,
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PTP_PIN_ACTION_CLOCK,
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PTP_PIN_ACTION_DELTA,
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PTP_PIN_ACTION_NOSYNC,
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PTP_PIN_ACTION_SYNC,
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};
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#define PTP_CFG_MISC_PTP_EN BIT(2)
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#define PSEC_PER_SEC 1000000000000LL
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#define PTP_CFG_CLK_ADJ_CFG_ENA BIT(0)
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#define PTP_CFG_CLK_ADJ_CFG_DIR BIT(1)
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#define PTP_CFG_CLK_ADJ_FREQ_NS BIT(30)
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#endif
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