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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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8cc7f5338e
Move the existing clock code in mach-msm to the common clock framework. We lose our capability to set the rate of and enable a clock through debugfs. This is ok though because the debugfs features are mainly used for testing and development of new clock code. To maintain compatibility with the original MSM clock code we make a wrapper for clk_reset() that calls the struct msm_clk specific reset function. This is necessary for the usb and sdcc devices on MSM until a better suited API is made available. Cc: Saravana Kannan <skannan@codeaurora.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: David Brown <davidb@codeaurora.org>
146 lines
4.7 KiB
C
146 lines
4.7 KiB
C
/*
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* Copyright (c) 2009-2012, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __ARCH_ARM_MACH_MSM_CLOCK_PCOM_H
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#define __ARCH_ARM_MACH_MSM_CLOCK_PCOM_H
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/* clock IDs used by the modem processor */
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#define P_ACPU_CLK 0 /* Applications processor clock */
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#define P_ADM_CLK 1 /* Applications data mover clock */
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#define P_ADSP_CLK 2 /* ADSP clock */
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#define P_EBI1_CLK 3 /* External bus interface 1 clock */
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#define P_EBI2_CLK 4 /* External bus interface 2 clock */
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#define P_ECODEC_CLK 5 /* External CODEC clock */
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#define P_EMDH_CLK 6 /* External MDDI host clock */
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#define P_GP_CLK 7 /* General purpose clock */
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#define P_GRP_3D_CLK 8 /* Graphics clock */
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#define P_I2C_CLK 9 /* I2C clock */
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#define P_ICODEC_RX_CLK 10 /* Internal CODEX RX clock */
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#define P_ICODEC_TX_CLK 11 /* Internal CODEX TX clock */
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#define P_IMEM_CLK 12 /* Internal graphics memory clock */
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#define P_MDC_CLK 13 /* MDDI client clock */
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#define P_MDP_CLK 14 /* Mobile display processor clock */
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#define P_PBUS_CLK 15 /* Peripheral bus clock */
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#define P_PCM_CLK 16 /* PCM clock */
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#define P_PMDH_CLK 17 /* Primary MDDI host clock */
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#define P_SDAC_CLK 18 /* Stereo DAC clock */
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#define P_SDC1_CLK 19 /* Secure Digital Card clocks */
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#define P_SDC1_P_CLK 20
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#define P_SDC2_CLK 21
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#define P_SDC2_P_CLK 22
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#define P_SDC3_CLK 23
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#define P_SDC3_P_CLK 24
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#define P_SDC4_CLK 25
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#define P_SDC4_P_CLK 26
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#define P_TSIF_CLK 27 /* Transport Stream Interface clocks */
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#define P_TSIF_REF_CLK 28
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#define P_TV_DAC_CLK 29 /* TV clocks */
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#define P_TV_ENC_CLK 30
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#define P_UART1_CLK 31 /* UART clocks */
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#define P_UART2_CLK 32
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#define P_UART3_CLK 33
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#define P_UART1DM_CLK 34
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#define P_UART2DM_CLK 35
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#define P_USB_HS_CLK 36 /* High speed USB core clock */
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#define P_USB_HS_P_CLK 37 /* High speed USB pbus clock */
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#define P_USB_OTG_CLK 38 /* Full speed USB clock */
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#define P_VDC_CLK 39 /* Video controller clock */
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#define P_VFE_MDC_CLK 40 /* Camera / Video Front End clock */
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#define P_VFE_CLK 41 /* VFE MDDI client clock */
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#define P_MDP_LCDC_PCLK_CLK 42
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#define P_MDP_LCDC_PAD_PCLK_CLK 43
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#define P_MDP_VSYNC_CLK 44
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#define P_SPI_CLK 45
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#define P_VFE_AXI_CLK 46
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#define P_USB_HS2_CLK 47 /* High speed USB 2 core clock */
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#define P_USB_HS2_P_CLK 48 /* High speed USB 2 pbus clock */
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#define P_USB_HS3_CLK 49 /* High speed USB 3 core clock */
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#define P_USB_HS3_P_CLK 50 /* High speed USB 3 pbus clock */
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#define P_GRP_3D_P_CLK 51 /* Graphics pbus clock */
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#define P_USB_PHY_CLK 52 /* USB PHY clock */
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#define P_USB_HS_CORE_CLK 53 /* High speed USB 1 core clock */
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#define P_USB_HS2_CORE_CLK 54 /* High speed USB 2 core clock */
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#define P_USB_HS3_CORE_CLK 55 /* High speed USB 3 core clock */
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#define P_CAM_M_CLK 56
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#define P_CAMIF_PAD_P_CLK 57
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#define P_GRP_2D_CLK 58
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#define P_GRP_2D_P_CLK 59
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#define P_I2S_CLK 60
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#define P_JPEG_CLK 61
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#define P_JPEG_P_CLK 62
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#define P_LPA_CODEC_CLK 63
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#define P_LPA_CORE_CLK 64
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#define P_LPA_P_CLK 65
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#define P_MDC_IO_CLK 66
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#define P_MDC_P_CLK 67
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#define P_MFC_CLK 68
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#define P_MFC_DIV2_CLK 69
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#define P_MFC_P_CLK 70
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#define P_QUP_I2C_CLK 71
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#define P_ROTATOR_IMEM_CLK 72
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#define P_ROTATOR_P_CLK 73
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#define P_VFE_CAMIF_CLK 74
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#define P_VFE_P_CLK 75
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#define P_VPE_CLK 76
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#define P_I2C_2_CLK 77
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#define P_MI2S_CODEC_RX_S_CLK 78
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#define P_MI2S_CODEC_RX_M_CLK 79
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#define P_MI2S_CODEC_TX_S_CLK 80
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#define P_MI2S_CODEC_TX_M_CLK 81
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#define P_PMDH_P_CLK 82
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#define P_EMDH_P_CLK 83
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#define P_SPI_P_CLK 84
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#define P_TSIF_P_CLK 85
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#define P_MDP_P_CLK 86
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#define P_SDAC_M_CLK 87
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#define P_MI2S_S_CLK 88
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#define P_MI2S_M_CLK 89
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#define P_AXI_ROTATOR_CLK 90
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#define P_HDMI_CLK 91
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#define P_CSI0_CLK 92
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#define P_CSI0_VFE_CLK 93
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#define P_CSI0_P_CLK 94
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#define P_CSI1_CLK 95
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#define P_CSI1_VFE_CLK 96
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#define P_CSI1_P_CLK 97
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#define P_GSBI_CLK 98
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#define P_GSBI_P_CLK 99
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#define P_CE_CLK 100 /* Crypto engine */
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#define P_CODEC_SSBI_CLK 101
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#define P_NR_CLKS 102
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struct clk_pcom_desc {
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unsigned id;
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const char *name;
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const char *con;
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const char *dev;
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unsigned long flags;
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};
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struct pcom_clk_pdata {
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struct clk_pcom_desc *lookup;
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u32 num_lookups;
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};
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#define CLK_PCOM(clk_name, clk_id, clk_dev, clk_flags) { \
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.id = P_##clk_id, \
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.name = #clk_id, \
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.con = clk_name, \
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.dev = clk_dev, \
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.flags = clk_flags, \
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}
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#endif
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