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3f1b66be4a
Add documentation to describe Xilinx ZynqMP reset driver bindings. Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
131 lines
4.2 KiB
C
131 lines
4.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2018 Xilinx, Inc.
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*/
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#ifndef _DT_BINDINGS_ZYNQMP_RESETS_H
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#define _DT_BINDINGS_ZYNQMP_RESETS_H
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#define ZYNQMP_RESET_PCIE_CFG 0
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#define ZYNQMP_RESET_PCIE_BRIDGE 1
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#define ZYNQMP_RESET_PCIE_CTRL 2
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#define ZYNQMP_RESET_DP 3
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#define ZYNQMP_RESET_SWDT_CRF 4
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#define ZYNQMP_RESET_AFI_FM5 5
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#define ZYNQMP_RESET_AFI_FM4 6
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#define ZYNQMP_RESET_AFI_FM3 7
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#define ZYNQMP_RESET_AFI_FM2 8
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#define ZYNQMP_RESET_AFI_FM1 9
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#define ZYNQMP_RESET_AFI_FM0 10
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#define ZYNQMP_RESET_GDMA 11
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#define ZYNQMP_RESET_GPU_PP1 12
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#define ZYNQMP_RESET_GPU_PP0 13
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#define ZYNQMP_RESET_GPU 14
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#define ZYNQMP_RESET_GT 15
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#define ZYNQMP_RESET_SATA 16
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#define ZYNQMP_RESET_ACPU3_PWRON 17
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#define ZYNQMP_RESET_ACPU2_PWRON 18
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#define ZYNQMP_RESET_ACPU1_PWRON 19
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#define ZYNQMP_RESET_ACPU0_PWRON 20
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#define ZYNQMP_RESET_APU_L2 21
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#define ZYNQMP_RESET_ACPU3 22
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#define ZYNQMP_RESET_ACPU2 23
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#define ZYNQMP_RESET_ACPU1 24
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#define ZYNQMP_RESET_ACPU0 25
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#define ZYNQMP_RESET_DDR 26
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#define ZYNQMP_RESET_APM_FPD 27
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#define ZYNQMP_RESET_SOFT 28
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#define ZYNQMP_RESET_GEM0 29
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#define ZYNQMP_RESET_GEM1 30
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#define ZYNQMP_RESET_GEM2 31
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#define ZYNQMP_RESET_GEM3 32
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#define ZYNQMP_RESET_QSPI 33
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#define ZYNQMP_RESET_UART0 34
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#define ZYNQMP_RESET_UART1 35
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#define ZYNQMP_RESET_SPI0 36
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#define ZYNQMP_RESET_SPI1 37
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#define ZYNQMP_RESET_SDIO0 38
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#define ZYNQMP_RESET_SDIO1 39
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#define ZYNQMP_RESET_CAN0 40
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#define ZYNQMP_RESET_CAN1 41
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#define ZYNQMP_RESET_I2C0 42
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#define ZYNQMP_RESET_I2C1 43
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#define ZYNQMP_RESET_TTC0 44
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#define ZYNQMP_RESET_TTC1 45
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#define ZYNQMP_RESET_TTC2 46
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#define ZYNQMP_RESET_TTC3 47
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#define ZYNQMP_RESET_SWDT_CRL 48
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#define ZYNQMP_RESET_NAND 49
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#define ZYNQMP_RESET_ADMA 50
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#define ZYNQMP_RESET_GPIO 51
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#define ZYNQMP_RESET_IOU_CC 52
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#define ZYNQMP_RESET_TIMESTAMP 53
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#define ZYNQMP_RESET_RPU_R50 54
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#define ZYNQMP_RESET_RPU_R51 55
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#define ZYNQMP_RESET_RPU_AMBA 56
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#define ZYNQMP_RESET_OCM 57
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#define ZYNQMP_RESET_RPU_PGE 58
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#define ZYNQMP_RESET_USB0_CORERESET 59
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#define ZYNQMP_RESET_USB1_CORERESET 60
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#define ZYNQMP_RESET_USB0_HIBERRESET 61
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#define ZYNQMP_RESET_USB1_HIBERRESET 62
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#define ZYNQMP_RESET_USB0_APB 63
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#define ZYNQMP_RESET_USB1_APB 64
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#define ZYNQMP_RESET_IPI 65
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#define ZYNQMP_RESET_APM_LPD 66
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#define ZYNQMP_RESET_RTC 67
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#define ZYNQMP_RESET_SYSMON 68
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#define ZYNQMP_RESET_AFI_FM6 69
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#define ZYNQMP_RESET_LPD_SWDT 70
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#define ZYNQMP_RESET_FPD 71
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#define ZYNQMP_RESET_RPU_DBG1 72
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#define ZYNQMP_RESET_RPU_DBG0 73
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#define ZYNQMP_RESET_DBG_LPD 74
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#define ZYNQMP_RESET_DBG_FPD 75
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#define ZYNQMP_RESET_APLL 76
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#define ZYNQMP_RESET_DPLL 77
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#define ZYNQMP_RESET_VPLL 78
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#define ZYNQMP_RESET_IOPLL 79
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#define ZYNQMP_RESET_RPLL 80
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#define ZYNQMP_RESET_GPO3_PL_0 81
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#define ZYNQMP_RESET_GPO3_PL_1 82
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#define ZYNQMP_RESET_GPO3_PL_2 83
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#define ZYNQMP_RESET_GPO3_PL_3 84
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#define ZYNQMP_RESET_GPO3_PL_4 85
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#define ZYNQMP_RESET_GPO3_PL_5 86
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#define ZYNQMP_RESET_GPO3_PL_6 87
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#define ZYNQMP_RESET_GPO3_PL_7 88
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#define ZYNQMP_RESET_GPO3_PL_8 89
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#define ZYNQMP_RESET_GPO3_PL_9 90
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#define ZYNQMP_RESET_GPO3_PL_10 91
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#define ZYNQMP_RESET_GPO3_PL_11 92
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#define ZYNQMP_RESET_GPO3_PL_12 93
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#define ZYNQMP_RESET_GPO3_PL_13 94
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#define ZYNQMP_RESET_GPO3_PL_14 95
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#define ZYNQMP_RESET_GPO3_PL_15 96
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#define ZYNQMP_RESET_GPO3_PL_16 97
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#define ZYNQMP_RESET_GPO3_PL_17 98
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#define ZYNQMP_RESET_GPO3_PL_18 99
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#define ZYNQMP_RESET_GPO3_PL_19 100
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#define ZYNQMP_RESET_GPO3_PL_20 101
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#define ZYNQMP_RESET_GPO3_PL_21 102
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#define ZYNQMP_RESET_GPO3_PL_22 103
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#define ZYNQMP_RESET_GPO3_PL_23 104
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#define ZYNQMP_RESET_GPO3_PL_24 105
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#define ZYNQMP_RESET_GPO3_PL_25 106
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#define ZYNQMP_RESET_GPO3_PL_26 107
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#define ZYNQMP_RESET_GPO3_PL_27 108
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#define ZYNQMP_RESET_GPO3_PL_28 109
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#define ZYNQMP_RESET_GPO3_PL_29 110
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#define ZYNQMP_RESET_GPO3_PL_30 111
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#define ZYNQMP_RESET_GPO3_PL_31 112
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#define ZYNQMP_RESET_RPU_LS 113
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#define ZYNQMP_RESET_PS_ONLY 114
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#define ZYNQMP_RESET_PL 115
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#define ZYNQMP_RESET_PS_PL0 116
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#define ZYNQMP_RESET_PS_PL1 117
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#define ZYNQMP_RESET_PS_PL2 118
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#define ZYNQMP_RESET_PS_PL3 119
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#endif
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