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85151a6b0b
The pll post divider code was using DIV_ROUND_UP when determining the divider value best suited to produce the target frequency. Using DIV_ROUND_CLOSEST will give us better divider values when the division results in a small remainder. Also, change the post divider clock over to the determine_rate api instead of round_rate. Signed-off-by: Simran Rai <ssimran@broadcom.com> Signed-off-by: Lori Hikichi <lori.hikichi@broadcom.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> |
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.. | ||
clk-bcm63xx.c | ||
clk-bcm281xx.c | ||
clk-bcm2835-aux.c | ||
clk-bcm2835.c | ||
clk-bcm21664.c | ||
clk-bcm53573-ilp.c | ||
clk-cygnus.c | ||
clk-hr2.c | ||
clk-iproc-armpll.c | ||
clk-iproc-asiu.c | ||
clk-iproc-pll.c | ||
clk-iproc.h | ||
clk-kona-setup.c | ||
clk-kona.c | ||
clk-kona.h | ||
clk-ns2.c | ||
clk-nsp.c | ||
clk-sr.c | ||
Kconfig | ||
Makefile |