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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-21 06:47:41 +07:00
8512e07487
All the conditional ugly register selection really wants to be cleaned up. Use a struct describing each pipe and its registers. This will also let us hide some of the oddments between platforms for any future merging of bits together. In particular the way the DPLL and FP registers randomly wander around. Signed-off-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
387 lines
9.7 KiB
C
387 lines
9.7 KiB
C
/**************************************************************************
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* Copyright (c) 2011, Intel Corporation.
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* All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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*
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**************************************************************************/
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#include <linux/backlight.h>
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#include <drm/drmP.h>
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#include <drm/drm.h>
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#include "gma_drm.h"
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#include "psb_drv.h"
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#include "psb_reg.h"
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#include "psb_intel_reg.h"
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#include "intel_bios.h"
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static int psb_output_init(struct drm_device *dev)
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{
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struct drm_psb_private *dev_priv = dev->dev_private;
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psb_intel_lvds_init(dev, &dev_priv->mode_dev);
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psb_intel_sdvo_init(dev, SDVOB);
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return 0;
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}
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#ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
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/*
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* Poulsbo Backlight Interfaces
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*/
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#define BLC_PWM_PRECISION_FACTOR 100 /* 10000000 */
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#define BLC_PWM_FREQ_CALC_CONSTANT 32
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#define MHz 1000000
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#define PSB_BLC_PWM_PRECISION_FACTOR 10
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#define PSB_BLC_MAX_PWM_REG_FREQ 0xFFFE
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#define PSB_BLC_MIN_PWM_REG_FREQ 0x2
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#define PSB_BACKLIGHT_PWM_POLARITY_BIT_CLEAR (0xFFFE)
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#define PSB_BACKLIGHT_PWM_CTL_SHIFT (16)
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static int psb_brightness;
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static struct backlight_device *psb_backlight_device;
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static int psb_get_brightness(struct backlight_device *bd)
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{
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/* return locally cached var instead of HW read (due to DPST etc.) */
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/* FIXME: ideally return actual value in case firmware fiddled with
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it */
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return psb_brightness;
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}
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static int psb_backlight_setup(struct drm_device *dev)
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{
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struct drm_psb_private *dev_priv = dev->dev_private;
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unsigned long core_clock;
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/* u32 bl_max_freq; */
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/* unsigned long value; */
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u16 bl_max_freq;
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uint32_t value;
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uint32_t blc_pwm_precision_factor;
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/* get bl_max_freq and pol from dev_priv*/
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if (!dev_priv->lvds_bl) {
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dev_err(dev->dev, "Has no valid LVDS backlight info\n");
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return -ENOENT;
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}
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bl_max_freq = dev_priv->lvds_bl->freq;
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blc_pwm_precision_factor = PSB_BLC_PWM_PRECISION_FACTOR;
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core_clock = dev_priv->core_freq;
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value = (core_clock * MHz) / BLC_PWM_FREQ_CALC_CONSTANT;
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value *= blc_pwm_precision_factor;
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value /= bl_max_freq;
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value /= blc_pwm_precision_factor;
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if (value > (unsigned long long)PSB_BLC_MAX_PWM_REG_FREQ ||
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value < (unsigned long long)PSB_BLC_MIN_PWM_REG_FREQ)
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return -ERANGE;
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else {
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value &= PSB_BACKLIGHT_PWM_POLARITY_BIT_CLEAR;
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REG_WRITE(BLC_PWM_CTL,
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(value << PSB_BACKLIGHT_PWM_CTL_SHIFT) | (value));
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}
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return 0;
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}
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static int psb_set_brightness(struct backlight_device *bd)
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{
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struct drm_device *dev = bl_get_data(psb_backlight_device);
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int level = bd->props.brightness;
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/* Percentage 1-100% being valid */
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if (level < 1)
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level = 1;
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psb_intel_lvds_set_brightness(dev, level);
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psb_brightness = level;
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return 0;
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}
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static const struct backlight_ops psb_ops = {
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.get_brightness = psb_get_brightness,
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.update_status = psb_set_brightness,
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};
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static int psb_backlight_init(struct drm_device *dev)
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{
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struct drm_psb_private *dev_priv = dev->dev_private;
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int ret;
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struct backlight_properties props;
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memset(&props, 0, sizeof(struct backlight_properties));
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props.max_brightness = 100;
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props.type = BACKLIGHT_PLATFORM;
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psb_backlight_device = backlight_device_register("psb-bl",
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NULL, (void *)dev, &psb_ops, &props);
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if (IS_ERR(psb_backlight_device))
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return PTR_ERR(psb_backlight_device);
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ret = psb_backlight_setup(dev);
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if (ret < 0) {
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backlight_device_unregister(psb_backlight_device);
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psb_backlight_device = NULL;
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return ret;
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}
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psb_backlight_device->props.brightness = 100;
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psb_backlight_device->props.max_brightness = 100;
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backlight_update_status(psb_backlight_device);
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dev_priv->backlight_device = psb_backlight_device;
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return 0;
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}
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#endif
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/*
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* Provide the Poulsbo specific chip logic and low level methods
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* for power management
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*/
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static void psb_init_pm(struct drm_device *dev)
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{
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struct drm_psb_private *dev_priv = dev->dev_private;
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u32 gating = PSB_RSGX32(PSB_CR_CLKGATECTL);
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gating &= ~3; /* Disable 2D clock gating */
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gating |= 1;
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PSB_WSGX32(gating, PSB_CR_CLKGATECTL);
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PSB_RSGX32(PSB_CR_CLKGATECTL);
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}
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/**
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* psb_save_display_registers - save registers lost on suspend
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* @dev: our DRM device
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*
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* Save the state we need in order to be able to restore the interface
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* upon resume from suspend
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*/
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static int psb_save_display_registers(struct drm_device *dev)
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{
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struct drm_psb_private *dev_priv = dev->dev_private;
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struct drm_crtc *crtc;
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struct drm_connector *connector;
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struct psb_state *regs = &dev_priv->regs.psb;
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/* Display arbitration control + watermarks */
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regs->saveDSPARB = PSB_RVDC32(DSPARB);
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regs->saveDSPFW1 = PSB_RVDC32(DSPFW1);
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regs->saveDSPFW2 = PSB_RVDC32(DSPFW2);
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regs->saveDSPFW3 = PSB_RVDC32(DSPFW3);
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regs->saveDSPFW4 = PSB_RVDC32(DSPFW4);
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regs->saveDSPFW5 = PSB_RVDC32(DSPFW5);
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regs->saveDSPFW6 = PSB_RVDC32(DSPFW6);
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regs->saveCHICKENBIT = PSB_RVDC32(DSPCHICKENBIT);
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/* Save crtc and output state */
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mutex_lock(&dev->mode_config.mutex);
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list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
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if (drm_helper_crtc_in_use(crtc))
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crtc->funcs->save(crtc);
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}
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list_for_each_entry(connector, &dev->mode_config.connector_list, head)
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connector->funcs->save(connector);
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mutex_unlock(&dev->mode_config.mutex);
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return 0;
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}
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/**
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* psb_restore_display_registers - restore lost register state
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* @dev: our DRM device
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*
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* Restore register state that was lost during suspend and resume.
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*/
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static int psb_restore_display_registers(struct drm_device *dev)
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{
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struct drm_psb_private *dev_priv = dev->dev_private;
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struct drm_crtc *crtc;
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struct drm_connector *connector;
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struct psb_state *regs = &dev_priv->regs.psb;
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/* Display arbitration + watermarks */
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PSB_WVDC32(regs->saveDSPARB, DSPARB);
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PSB_WVDC32(regs->saveDSPFW1, DSPFW1);
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PSB_WVDC32(regs->saveDSPFW2, DSPFW2);
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PSB_WVDC32(regs->saveDSPFW3, DSPFW3);
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PSB_WVDC32(regs->saveDSPFW4, DSPFW4);
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PSB_WVDC32(regs->saveDSPFW5, DSPFW5);
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PSB_WVDC32(regs->saveDSPFW6, DSPFW6);
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PSB_WVDC32(regs->saveCHICKENBIT, DSPCHICKENBIT);
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/*make sure VGA plane is off. it initializes to on after reset!*/
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PSB_WVDC32(0x80000000, VGACNTRL);
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mutex_lock(&dev->mode_config.mutex);
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list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
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if (drm_helper_crtc_in_use(crtc))
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crtc->funcs->restore(crtc);
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list_for_each_entry(connector, &dev->mode_config.connector_list, head)
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connector->funcs->restore(connector);
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mutex_unlock(&dev->mode_config.mutex);
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return 0;
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}
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static int psb_power_down(struct drm_device *dev)
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{
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return 0;
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}
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static int psb_power_up(struct drm_device *dev)
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{
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return 0;
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}
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static void psb_get_core_freq(struct drm_device *dev)
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{
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uint32_t clock;
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struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
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struct drm_psb_private *dev_priv = dev->dev_private;
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/*pci_write_config_dword(pci_root, 0xD4, 0x00C32004);*/
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/*pci_write_config_dword(pci_root, 0xD0, 0xE0033000);*/
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pci_write_config_dword(pci_root, 0xD0, 0xD0050300);
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pci_read_config_dword(pci_root, 0xD4, &clock);
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pci_dev_put(pci_root);
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switch (clock & 0x07) {
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case 0:
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dev_priv->core_freq = 100;
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break;
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case 1:
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dev_priv->core_freq = 133;
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break;
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case 2:
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dev_priv->core_freq = 150;
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break;
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case 3:
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dev_priv->core_freq = 178;
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break;
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case 4:
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dev_priv->core_freq = 200;
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break;
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case 5:
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case 6:
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case 7:
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dev_priv->core_freq = 266;
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default:
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dev_priv->core_freq = 0;
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}
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}
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/* Poulsbo */
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static const struct psb_offset psb_regmap[2] = {
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{
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.fp0 = FPA0,
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.fp1 = FPA1,
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.cntr = DSPACNTR,
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.conf = PIPEACONF,
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.src = PIPEASRC,
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.dpll = DPLL_A,
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.htotal = HTOTAL_A,
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.hblank = HBLANK_A,
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.hsync = HSYNC_A,
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.vtotal = VTOTAL_A,
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.vblank = VBLANK_A,
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.vsync = VSYNC_A,
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.stride = DSPASTRIDE,
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.size = DSPASIZE,
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.pos = DSPAPOS,
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.base = DSPABASE,
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.surf = DSPASURF,
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.addr = DSPABASE,
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.status = PIPEASTAT,
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.linoff = DSPALINOFF,
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.tileoff = DSPATILEOFF,
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.palette = PALETTE_A,
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},
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{
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.fp0 = FPB0,
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.fp1 = FPB1,
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.cntr = DSPBCNTR,
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.conf = PIPEBCONF,
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.src = PIPEBSRC,
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.dpll = DPLL_B,
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.htotal = HTOTAL_B,
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.hblank = HBLANK_B,
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.hsync = HSYNC_B,
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.vtotal = VTOTAL_B,
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.vblank = VBLANK_B,
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.vsync = VSYNC_B,
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.stride = DSPBSTRIDE,
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.size = DSPBSIZE,
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.pos = DSPBPOS,
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.base = DSPBBASE,
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.surf = DSPBSURF,
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.addr = DSPBBASE,
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.status = PIPEBSTAT,
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.linoff = DSPBLINOFF,
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.tileoff = DSPBTILEOFF,
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.palette = PALETTE_B,
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}
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};
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static int psb_chip_setup(struct drm_device *dev)
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{
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struct drm_psb_private *dev_priv = dev->dev_private;
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dev_priv->regmap = psb_regmap;
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psb_get_core_freq(dev);
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gma_intel_setup_gmbus(dev);
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psb_intel_opregion_init(dev);
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psb_intel_init_bios(dev);
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return 0;
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}
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static void psb_chip_teardown(struct drm_device *dev)
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{
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gma_intel_teardown_gmbus(dev);
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}
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const struct psb_ops psb_chip_ops = {
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.name = "Poulsbo",
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.accel_2d = 1,
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.pipes = 2,
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.crtcs = 2,
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.hdmi_mask = (1 << 0),
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.lvds_mask = (1 << 1),
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.sgx_offset = PSB_SGX_OFFSET,
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.chip_setup = psb_chip_setup,
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.chip_teardown = psb_chip_teardown,
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.crtc_helper = &psb_intel_helper_funcs,
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.crtc_funcs = &psb_intel_crtc_funcs,
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.output_init = psb_output_init,
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#ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
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.backlight_init = psb_backlight_init,
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#endif
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.init_pm = psb_init_pm,
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.save_regs = psb_save_display_registers,
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.restore_regs = psb_restore_display_registers,
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.power_down = psb_power_down,
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.power_up = psb_power_up,
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};
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