mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-22 20:24:29 +07:00
638298dc66
Haswell LynxPoint and LynxPoint-LP with the recent Intel BIOS show
mysterious wakeups after shutdown occasionally. After discussing with
BIOS engineers, they explained that the new BIOS expects that the
wakeup sources are cleared and set to D3 for all wakeup devices when
the system is going to sleep or power off, but the current xhci driver
doesn't do this properly (partly intentionally).
This patch introduces a new quirk, XHCI_SPURIOUS_WAKEUP, for
fixing the spurious wakeups at S5 by calling xhci_reset() in the xhci
shutdown ops as done in xhci_stop(), and setting the device to PCI D3
at shutdown and remove ops.
The PCI D3 call is based on the initial fix patch by Oliver Neukum.
[Note: Sarah changed the quirk name from XHCI_HSW_SPURIOUS_WAKEUP to
XHCI_SPURIOUS_WAKEUP, since none of the other quirks have system names
in them. Sarah also fixed a collision with a quirk submitted around the
same time, by changing the xhci->quirks bit from 17 to 18.]
This patch should be backported to kernels as old as 3.0, that
contain the commit 1c12443ab8
"xhci: Add
Lynx Point to list of Intel switchable hosts."
Cc: Oliver Neukum <oneukum@suse.de>
Signed-off-by: Takashi Iwai <tiwai@suse.de>
Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
Cc: stable@vger.kernel.org
395 lines
12 KiB
C
395 lines
12 KiB
C
/*
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* xHCI host controller driver PCI Bus Glue.
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*
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* Copyright (C) 2008 Intel Corp.
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*
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* Author: Sarah Sharp
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* Some code borrowed from the Linux EHCI driver.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software Foundation,
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* Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/pci.h>
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#include <linux/slab.h>
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#include <linux/module.h>
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#include "xhci.h"
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#include "xhci-trace.h"
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/* Device for a quirk */
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#define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73
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#define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000
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#define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400
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#define PCI_VENDOR_ID_ETRON 0x1b6f
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#define PCI_DEVICE_ID_ASROCK_P67 0x7023
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#define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31
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#define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31
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static const char hcd_name[] = "xhci_hcd";
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/* called after powerup, by probe or system-pm "wakeup" */
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static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
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{
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/*
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* TODO: Implement finding debug ports later.
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* TODO: see if there are any quirks that need to be added to handle
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* new extended capabilities.
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*/
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/* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
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if (!pci_set_mwi(pdev))
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xhci_dbg(xhci, "MWI active\n");
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xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
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return 0;
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}
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static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
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{
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struct pci_dev *pdev = to_pci_dev(dev);
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/* Look for vendor-specific quirks */
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if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
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(pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK ||
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pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
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if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
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pdev->revision == 0x0) {
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xhci->quirks |= XHCI_RESET_EP_QUIRK;
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xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
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"QUIRK: Fresco Logic xHC needs configure"
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" endpoint cmd after reset endpoint");
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}
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if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
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pdev->revision == 0x4) {
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xhci->quirks |= XHCI_SLOW_SUSPEND;
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xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
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"QUIRK: Fresco Logic xHC revision %u"
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"must be suspended extra slowly",
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pdev->revision);
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}
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/* Fresco Logic confirms: all revisions of this chip do not
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* support MSI, even though some of them claim to in their PCI
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* capabilities.
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*/
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xhci->quirks |= XHCI_BROKEN_MSI;
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xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
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"QUIRK: Fresco Logic revision %u "
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"has broken MSI implementation",
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pdev->revision);
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xhci->quirks |= XHCI_TRUST_TX_LENGTH;
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}
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if (pdev->vendor == PCI_VENDOR_ID_NEC)
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xhci->quirks |= XHCI_NEC_HOST;
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if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
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xhci->quirks |= XHCI_AMD_0x96_HOST;
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/* AMD PLL quirk */
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if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info())
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xhci->quirks |= XHCI_AMD_PLL_FIX;
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if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
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xhci->quirks |= XHCI_LPM_SUPPORT;
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xhci->quirks |= XHCI_INTEL_HOST;
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}
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if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
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pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
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xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
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xhci->limit_active_eps = 64;
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xhci->quirks |= XHCI_SW_BW_CHECKING;
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/*
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* PPT desktop boards DH77EB and DH77DF will power back on after
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* a few seconds of being shutdown. The fix for this is to
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* switch the ports from xHCI to EHCI on shutdown. We can't use
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* DMI information to find those particular boards (since each
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* vendor will change the board name), so we have to key off all
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* PPT chipsets.
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*/
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xhci->quirks |= XHCI_SPURIOUS_REBOOT;
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xhci->quirks |= XHCI_AVOID_BEI;
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}
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if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
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(pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI ||
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pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI)) {
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/* Workaround for occasional spurious wakeups from S5 (or
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* any other sleep) on Haswell machines with LPT and LPT-LP
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* with the new Intel BIOS
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*/
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xhci->quirks |= XHCI_SPURIOUS_WAKEUP;
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}
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if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
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pdev->device == PCI_DEVICE_ID_ASROCK_P67) {
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xhci->quirks |= XHCI_RESET_ON_RESUME;
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xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
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"QUIRK: Resetting on resume");
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xhci->quirks |= XHCI_TRUST_TX_LENGTH;
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}
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if (pdev->vendor == PCI_VENDOR_ID_VIA)
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xhci->quirks |= XHCI_RESET_ON_RESUME;
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}
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/* called during probe() after chip reset completes */
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static int xhci_pci_setup(struct usb_hcd *hcd)
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{
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struct xhci_hcd *xhci;
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struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
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int retval;
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retval = xhci_gen_setup(hcd, xhci_pci_quirks);
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if (retval)
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return retval;
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xhci = hcd_to_xhci(hcd);
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if (!usb_hcd_is_primary_hcd(hcd))
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return 0;
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pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
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xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
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/* Find any debug ports */
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retval = xhci_pci_reinit(xhci, pdev);
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if (!retval)
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return retval;
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kfree(xhci);
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return retval;
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}
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/*
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* We need to register our own PCI probe function (instead of the USB core's
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* function) in order to create a second roothub under xHCI.
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*/
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static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
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{
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int retval;
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struct xhci_hcd *xhci;
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struct hc_driver *driver;
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struct usb_hcd *hcd;
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driver = (struct hc_driver *)id->driver_data;
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/* Register the USB 2.0 roothub.
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* FIXME: USB core must know to register the USB 2.0 roothub first.
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* This is sort of silly, because we could just set the HCD driver flags
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* to say USB 2.0, but I'm not sure what the implications would be in
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* the other parts of the HCD code.
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*/
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retval = usb_hcd_pci_probe(dev, id);
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if (retval)
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return retval;
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/* USB 2.0 roothub is stored in the PCI device now. */
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hcd = dev_get_drvdata(&dev->dev);
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xhci = hcd_to_xhci(hcd);
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xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev,
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pci_name(dev), hcd);
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if (!xhci->shared_hcd) {
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retval = -ENOMEM;
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goto dealloc_usb2_hcd;
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}
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/* Set the xHCI pointer before xhci_pci_setup() (aka hcd_driver.reset)
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* is called by usb_add_hcd().
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*/
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*((struct xhci_hcd **) xhci->shared_hcd->hcd_priv) = xhci;
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retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
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IRQF_SHARED);
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if (retval)
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goto put_usb3_hcd;
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/* Roothub already marked as USB 3.0 speed */
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/* We know the LPM timeout algorithms for this host, let the USB core
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* enable and disable LPM for devices under the USB 3.0 roothub.
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*/
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if (xhci->quirks & XHCI_LPM_SUPPORT)
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hcd_to_bus(xhci->shared_hcd)->root_hub->lpm_capable = 1;
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return 0;
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put_usb3_hcd:
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usb_put_hcd(xhci->shared_hcd);
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dealloc_usb2_hcd:
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usb_hcd_pci_remove(dev);
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return retval;
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}
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static void xhci_pci_remove(struct pci_dev *dev)
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{
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struct xhci_hcd *xhci;
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xhci = hcd_to_xhci(pci_get_drvdata(dev));
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if (xhci->shared_hcd) {
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usb_remove_hcd(xhci->shared_hcd);
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usb_put_hcd(xhci->shared_hcd);
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}
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usb_hcd_pci_remove(dev);
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/* Workaround for spurious wakeups at shutdown with HSW */
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if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
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pci_set_power_state(dev, PCI_D3hot);
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kfree(xhci);
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}
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#ifdef CONFIG_PM
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static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
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{
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struct xhci_hcd *xhci = hcd_to_xhci(hcd);
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struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
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/*
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* Systems with the TI redriver that loses port status change events
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* need to have the registers polled during D3, so avoid D3cold.
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*/
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if (xhci_compliance_mode_recovery_timer_quirk_check())
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pdev->no_d3cold = true;
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return xhci_suspend(xhci);
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}
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static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
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{
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struct xhci_hcd *xhci = hcd_to_xhci(hcd);
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struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
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int retval = 0;
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/* The BIOS on systems with the Intel Panther Point chipset may or may
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* not support xHCI natively. That means that during system resume, it
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* may switch the ports back to EHCI so that users can use their
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* keyboard to select a kernel from GRUB after resume from hibernate.
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*
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* The BIOS is supposed to remember whether the OS had xHCI ports
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* enabled before resume, and switch the ports back to xHCI when the
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* BIOS/OS semaphore is written, but we all know we can't trust BIOS
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* writers.
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*
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* Unconditionally switch the ports back to xHCI after a system resume.
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* It should not matter whether the EHCI or xHCI controller is
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* resumed first. It's enough to do the switchover in xHCI because
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* USB core won't notice anything as the hub driver doesn't start
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* running again until after all the devices (including both EHCI and
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* xHCI host controllers) have been resumed.
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*/
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if (pdev->vendor == PCI_VENDOR_ID_INTEL)
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usb_enable_intel_xhci_ports(pdev);
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retval = xhci_resume(xhci, hibernated);
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return retval;
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}
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#endif /* CONFIG_PM */
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static const struct hc_driver xhci_pci_hc_driver = {
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.description = hcd_name,
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.product_desc = "xHCI Host Controller",
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.hcd_priv_size = sizeof(struct xhci_hcd *),
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/*
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* generic hardware linkage
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*/
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.irq = xhci_irq,
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.flags = HCD_MEMORY | HCD_USB3 | HCD_SHARED,
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/*
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* basic lifecycle operations
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*/
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.reset = xhci_pci_setup,
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.start = xhci_run,
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#ifdef CONFIG_PM
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.pci_suspend = xhci_pci_suspend,
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.pci_resume = xhci_pci_resume,
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#endif
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.stop = xhci_stop,
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.shutdown = xhci_shutdown,
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/*
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* managing i/o requests and associated device resources
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*/
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.urb_enqueue = xhci_urb_enqueue,
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.urb_dequeue = xhci_urb_dequeue,
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.alloc_dev = xhci_alloc_dev,
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.free_dev = xhci_free_dev,
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.alloc_streams = xhci_alloc_streams,
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.free_streams = xhci_free_streams,
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.add_endpoint = xhci_add_endpoint,
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.drop_endpoint = xhci_drop_endpoint,
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.endpoint_reset = xhci_endpoint_reset,
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.check_bandwidth = xhci_check_bandwidth,
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.reset_bandwidth = xhci_reset_bandwidth,
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.address_device = xhci_address_device,
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.update_hub_device = xhci_update_hub_device,
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.reset_device = xhci_discover_or_reset_device,
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/*
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* scheduling support
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*/
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.get_frame_number = xhci_get_frame,
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/* Root hub support */
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.hub_control = xhci_hub_control,
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.hub_status_data = xhci_hub_status_data,
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.bus_suspend = xhci_bus_suspend,
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.bus_resume = xhci_bus_resume,
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/*
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* call back when device connected and addressed
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*/
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.update_device = xhci_update_device,
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.set_usb2_hw_lpm = xhci_set_usb2_hardware_lpm,
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.enable_usb3_lpm_timeout = xhci_enable_usb3_lpm_timeout,
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.disable_usb3_lpm_timeout = xhci_disable_usb3_lpm_timeout,
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.find_raw_port_number = xhci_find_raw_port_number,
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};
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/*-------------------------------------------------------------------------*/
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/* PCI driver selection metadata; PCI hotplugging uses this */
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static const struct pci_device_id pci_ids[] = { {
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/* handle any USB 3.0 xHCI controller */
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PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
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.driver_data = (unsigned long) &xhci_pci_hc_driver,
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},
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{ /* end: all zeroes */ }
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};
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MODULE_DEVICE_TABLE(pci, pci_ids);
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/* pci driver glue; this is a "new style" PCI driver module */
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static struct pci_driver xhci_pci_driver = {
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.name = (char *) hcd_name,
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.id_table = pci_ids,
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.probe = xhci_pci_probe,
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.remove = xhci_pci_remove,
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/* suspend and resume implemented later */
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.shutdown = usb_hcd_pci_shutdown,
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#ifdef CONFIG_PM
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.driver = {
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.pm = &usb_hcd_pci_pm_ops
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},
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#endif
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};
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int __init xhci_register_pci(void)
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{
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return pci_register_driver(&xhci_pci_driver);
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}
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void xhci_unregister_pci(void)
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{
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pci_unregister_driver(&xhci_pci_driver);
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}
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