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44d524218c
The global timer IRQ (PPI[0], PPI 11 in device tree terms) is a
rising edge interrupt. The ARM Cortex-A5 MPCore TRM in Chapter
10.1.2. Interrupt types and sources says:
"Interrupt is rising-edge sensitive."
The bits seem to be read-only, hence this missconfiguration had
no negative effect. However, with commit 992345a58e
("irqchip/gic: WARN if setting the interrupt type for a PPI fails")
warnings such as this get printed:
GIC: PPI11 is secure or misconfigured
With this change the new configuration matches the default
configuration and no warning is printed anymore.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
98 lines
2.9 KiB
Plaintext
98 lines
2.9 KiB
Plaintext
/*
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* Copyright 2013 Freescale Semiconductor, Inc.
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This file is distributed in the hope that it will be useful
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "skeleton.dtsi"
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#include "vfxxx.dtsi"
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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a5_cpu: cpu@0 {
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compatible = "arm,cortex-a5";
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device_type = "cpu";
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reg = <0x0>;
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};
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};
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soc {
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aips-bus@40000000 {
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intc: interrupt-controller@40002000 {
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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interrupt-parent = <&intc>;
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reg = <0x40003000 0x1000>,
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<0x40002100 0x100>;
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};
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global_timer: timer@40002200 {
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compatible = "arm,cortex-a9-global-timer";
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reg = <0x40002200 0x20>;
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interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
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interrupt-parent = <&intc>;
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clocks = <&clks VF610_CLK_PLATFORM_BUS>;
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};
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};
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aips-bus@40080000 {
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pmu@40089000 {
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compatible = "arm,cortex-a5-pmu";
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interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&a5_cpu>;
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reg = <0x40089000 0x1000>;
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};
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};
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};
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};
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&mscm_ir {
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interrupt-parent = <&intc>;
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};
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&wdoga5 {
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status = "okay";
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};
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