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8c37bb3ac9
The __cpuinit type of throwaway sections might have made sense
some time ago when RAM was more constrained, but now the savings
do not offset the cost and complications. For example, the fix in
commit 5e427ec2d0 ("x86: Fix bit corruption at CPU resume time")
is a good example of the nasty type of bugs that can be created
with improper use of the various __init prefixes.
After a discussion on LKML[1] it was decided that cpuinit should go
the way of devinit and be phased out. Once all the users are gone,
we can then finally remove the macros themselves from linux/init.h.
This removes all the drivers/clocksource and drivers/irqchip uses of
the __cpuinit macros from all C files.
[1] https://lkml.org/lkml/2013/5/20/589
Cc: John Stultz <john.stultz@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
302 lines
7.7 KiB
C
302 lines
7.7 KiB
C
/*
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* Marvell Armada 370/XP SoC timer handling.
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*
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* Copyright (C) 2012 Marvell
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*
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* Lior Amsalem <alior@marvell.com>
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*
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* Timer 0 is used as free-running clocksource, while timer 1 is
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* used as clock_event_device.
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*/
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/kernel.h>
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#include <linux/clk.h>
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#include <linux/timer.h>
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#include <linux/clockchips.h>
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#include <linux/interrupt.h>
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#include <linux/of.h>
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#include <linux/of_irq.h>
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#include <linux/of_address.h>
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#include <linux/irq.h>
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#include <linux/module.h>
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#include <linux/sched_clock.h>
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#include <asm/localtimer.h>
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#include <linux/percpu.h>
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/*
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* Timer block registers.
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*/
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#define TIMER_CTRL_OFF 0x0000
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#define TIMER0_EN 0x0001
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#define TIMER0_RELOAD_EN 0x0002
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#define TIMER0_25MHZ 0x0800
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#define TIMER0_DIV(div) ((div) << 19)
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#define TIMER1_EN 0x0004
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#define TIMER1_RELOAD_EN 0x0008
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#define TIMER1_25MHZ 0x1000
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#define TIMER1_DIV(div) ((div) << 22)
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#define TIMER_EVENTS_STATUS 0x0004
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#define TIMER0_CLR_MASK (~0x1)
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#define TIMER1_CLR_MASK (~0x100)
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#define TIMER0_RELOAD_OFF 0x0010
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#define TIMER0_VAL_OFF 0x0014
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#define TIMER1_RELOAD_OFF 0x0018
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#define TIMER1_VAL_OFF 0x001c
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#define LCL_TIMER_EVENTS_STATUS 0x0028
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/* Global timers are connected to the coherency fabric clock, and the
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below divider reduces their incrementing frequency. */
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#define TIMER_DIVIDER_SHIFT 5
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#define TIMER_DIVIDER (1 << TIMER_DIVIDER_SHIFT)
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/*
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* SoC-specific data.
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*/
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static void __iomem *timer_base, *local_base;
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static unsigned int timer_clk;
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static bool timer25Mhz = true;
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/*
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* Number of timer ticks per jiffy.
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*/
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static u32 ticks_per_jiffy;
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static struct clock_event_device __percpu **percpu_armada_370_xp_evt;
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static u32 notrace armada_370_xp_read_sched_clock(void)
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{
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return ~readl(timer_base + TIMER0_VAL_OFF);
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}
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/*
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* Clockevent handling.
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*/
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static int
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armada_370_xp_clkevt_next_event(unsigned long delta,
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struct clock_event_device *dev)
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{
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u32 u;
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/*
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* Clear clockevent timer interrupt.
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*/
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writel(TIMER0_CLR_MASK, local_base + LCL_TIMER_EVENTS_STATUS);
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/*
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* Setup new clockevent timer value.
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*/
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writel(delta, local_base + TIMER0_VAL_OFF);
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/*
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* Enable the timer.
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*/
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u = readl(local_base + TIMER_CTRL_OFF);
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u = ((u & ~TIMER0_RELOAD_EN) | TIMER0_EN |
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TIMER0_DIV(TIMER_DIVIDER_SHIFT));
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writel(u, local_base + TIMER_CTRL_OFF);
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return 0;
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}
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static void
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armada_370_xp_clkevt_mode(enum clock_event_mode mode,
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struct clock_event_device *dev)
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{
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u32 u;
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if (mode == CLOCK_EVT_MODE_PERIODIC) {
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/*
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* Setup timer to fire at 1/HZ intervals.
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*/
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writel(ticks_per_jiffy - 1, local_base + TIMER0_RELOAD_OFF);
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writel(ticks_per_jiffy - 1, local_base + TIMER0_VAL_OFF);
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/*
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* Enable timer.
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*/
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u = readl(local_base + TIMER_CTRL_OFF);
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writel((u | TIMER0_EN | TIMER0_RELOAD_EN |
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TIMER0_DIV(TIMER_DIVIDER_SHIFT)),
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local_base + TIMER_CTRL_OFF);
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} else {
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/*
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* Disable timer.
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*/
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u = readl(local_base + TIMER_CTRL_OFF);
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writel(u & ~TIMER0_EN, local_base + TIMER_CTRL_OFF);
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/*
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* ACK pending timer interrupt.
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*/
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writel(TIMER0_CLR_MASK, local_base + LCL_TIMER_EVENTS_STATUS);
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}
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}
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static struct clock_event_device armada_370_xp_clkevt = {
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.name = "armada_370_xp_per_cpu_tick",
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.features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
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.shift = 32,
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.rating = 300,
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.set_next_event = armada_370_xp_clkevt_next_event,
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.set_mode = armada_370_xp_clkevt_mode,
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};
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static irqreturn_t armada_370_xp_timer_interrupt(int irq, void *dev_id)
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{
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/*
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* ACK timer interrupt and call event handler.
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*/
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struct clock_event_device *evt = *(struct clock_event_device **)dev_id;
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writel(TIMER0_CLR_MASK, local_base + LCL_TIMER_EVENTS_STATUS);
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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/*
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* Setup the local clock events for a CPU.
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*/
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static int armada_370_xp_timer_setup(struct clock_event_device *evt)
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{
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u32 u;
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int cpu = smp_processor_id();
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/* Use existing clock_event for cpu 0 */
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if (!smp_processor_id())
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return 0;
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u = readl(local_base + TIMER_CTRL_OFF);
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if (timer25Mhz)
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writel(u | TIMER0_25MHZ, local_base + TIMER_CTRL_OFF);
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else
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writel(u & ~TIMER0_25MHZ, local_base + TIMER_CTRL_OFF);
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evt->name = armada_370_xp_clkevt.name;
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evt->irq = armada_370_xp_clkevt.irq;
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evt->features = armada_370_xp_clkevt.features;
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evt->shift = armada_370_xp_clkevt.shift;
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evt->rating = armada_370_xp_clkevt.rating,
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evt->set_next_event = armada_370_xp_clkevt_next_event,
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evt->set_mode = armada_370_xp_clkevt_mode,
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evt->cpumask = cpumask_of(cpu);
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*__this_cpu_ptr(percpu_armada_370_xp_evt) = evt;
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clockevents_config_and_register(evt, timer_clk, 1, 0xfffffffe);
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enable_percpu_irq(evt->irq, 0);
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return 0;
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}
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static void armada_370_xp_timer_stop(struct clock_event_device *evt)
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{
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evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
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disable_percpu_irq(evt->irq);
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}
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static struct local_timer_ops armada_370_xp_local_timer_ops = {
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.setup = armada_370_xp_timer_setup,
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.stop = armada_370_xp_timer_stop,
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};
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void __init armada_370_xp_timer_init(void)
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{
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u32 u;
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struct device_node *np;
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int res;
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np = of_find_compatible_node(NULL, NULL, "marvell,armada-370-xp-timer");
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timer_base = of_iomap(np, 0);
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WARN_ON(!timer_base);
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local_base = of_iomap(np, 1);
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if (of_find_property(np, "marvell,timer-25Mhz", NULL)) {
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/* The fixed 25MHz timer is available so let's use it */
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u = readl(local_base + TIMER_CTRL_OFF);
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writel(u | TIMER0_25MHZ,
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local_base + TIMER_CTRL_OFF);
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u = readl(timer_base + TIMER_CTRL_OFF);
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writel(u | TIMER0_25MHZ,
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timer_base + TIMER_CTRL_OFF);
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timer_clk = 25000000;
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} else {
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unsigned long rate = 0;
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struct clk *clk = of_clk_get(np, 0);
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WARN_ON(IS_ERR(clk));
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rate = clk_get_rate(clk);
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u = readl(local_base + TIMER_CTRL_OFF);
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writel(u & ~(TIMER0_25MHZ),
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local_base + TIMER_CTRL_OFF);
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u = readl(timer_base + TIMER_CTRL_OFF);
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writel(u & ~(TIMER0_25MHZ),
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timer_base + TIMER_CTRL_OFF);
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timer_clk = rate / TIMER_DIVIDER;
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timer25Mhz = false;
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}
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/*
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* We use timer 0 as clocksource, and private(local) timer 0
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* for clockevents
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*/
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armada_370_xp_clkevt.irq = irq_of_parse_and_map(np, 4);
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ticks_per_jiffy = (timer_clk + HZ / 2) / HZ;
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/*
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* Set scale and timer for sched_clock.
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*/
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setup_sched_clock(armada_370_xp_read_sched_clock, 32, timer_clk);
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/*
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* Setup free-running clocksource timer (interrupts
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* disabled).
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*/
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writel(0xffffffff, timer_base + TIMER0_VAL_OFF);
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writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF);
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u = readl(timer_base + TIMER_CTRL_OFF);
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writel((u | TIMER0_EN | TIMER0_RELOAD_EN |
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TIMER0_DIV(TIMER_DIVIDER_SHIFT)), timer_base + TIMER_CTRL_OFF);
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clocksource_mmio_init(timer_base + TIMER0_VAL_OFF,
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"armada_370_xp_clocksource",
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timer_clk, 300, 32, clocksource_mmio_readl_down);
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/* Register the clockevent on the private timer of CPU 0 */
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armada_370_xp_clkevt.cpumask = cpumask_of(0);
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clockevents_config_and_register(&armada_370_xp_clkevt,
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timer_clk, 1, 0xfffffffe);
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percpu_armada_370_xp_evt = alloc_percpu(struct clock_event_device *);
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/*
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* Setup clockevent timer (interrupt-driven).
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*/
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*__this_cpu_ptr(percpu_armada_370_xp_evt) = &armada_370_xp_clkevt;
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res = request_percpu_irq(armada_370_xp_clkevt.irq,
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armada_370_xp_timer_interrupt,
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armada_370_xp_clkevt.name,
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percpu_armada_370_xp_evt);
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if (!res) {
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enable_percpu_irq(armada_370_xp_clkevt.irq, 0);
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#ifdef CONFIG_LOCAL_TIMERS
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local_timer_register(&armada_370_xp_local_timer_ops);
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#endif
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}
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}
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