mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-02 20:26:41 +07:00
1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
150 lines
3.9 KiB
C
150 lines
3.9 KiB
C
#ifndef _M68K_CACHEFLUSH_H
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#define _M68K_CACHEFLUSH_H
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#include <linux/mm.h>
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/*
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* Cache handling functions
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*/
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#define flush_icache() \
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({ \
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if (CPU_IS_040_OR_060) \
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__asm__ __volatile__("nop\n\t" \
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".chip 68040\n\t" \
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"cinva %%ic\n\t" \
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".chip 68k" : ); \
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else { \
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unsigned long _tmp; \
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__asm__ __volatile__("movec %%cacr,%0\n\t" \
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"orw %1,%0\n\t" \
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"movec %0,%%cacr" \
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: "=&d" (_tmp) \
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: "id" (FLUSH_I)); \
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} \
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})
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/*
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* invalidate the cache for the specified memory range.
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* It starts at the physical address specified for
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* the given number of bytes.
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*/
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extern void cache_clear(unsigned long paddr, int len);
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/*
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* push any dirty cache in the specified memory range.
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* It starts at the physical address specified for
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* the given number of bytes.
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*/
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extern void cache_push(unsigned long paddr, int len);
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/*
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* push and invalidate pages in the specified user virtual
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* memory range.
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*/
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extern void cache_push_v(unsigned long vaddr, int len);
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/* cache code */
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#define FLUSH_I_AND_D (0x00000808)
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#define FLUSH_I (0x00000008)
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/* This is needed whenever the virtual mapping of the current
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process changes. */
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#define __flush_cache_all() \
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({ \
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if (CPU_IS_040_OR_060) \
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__asm__ __volatile__("nop\n\t" \
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".chip 68040\n\t" \
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"cpusha %dc\n\t" \
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".chip 68k"); \
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else { \
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unsigned long _tmp; \
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__asm__ __volatile__("movec %%cacr,%0\n\t" \
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"orw %1,%0\n\t" \
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"movec %0,%%cacr" \
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: "=&d" (_tmp) \
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: "di" (FLUSH_I_AND_D)); \
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} \
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})
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#define __flush_cache_030() \
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({ \
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if (CPU_IS_020_OR_030) { \
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unsigned long _tmp; \
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__asm__ __volatile__("movec %%cacr,%0\n\t" \
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"orw %1,%0\n\t" \
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"movec %0,%%cacr" \
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: "=&d" (_tmp) \
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: "di" (FLUSH_I_AND_D)); \
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} \
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})
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#define flush_cache_all() __flush_cache_all()
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#define flush_cache_vmap(start, end) flush_cache_all()
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#define flush_cache_vunmap(start, end) flush_cache_all()
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static inline void flush_cache_mm(struct mm_struct *mm)
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{
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if (mm == current->mm)
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__flush_cache_030();
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}
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/* flush_cache_range/flush_cache_page must be macros to avoid
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a dependency on linux/mm.h, which includes this file... */
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static inline void flush_cache_range(struct vm_area_struct *vma,
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unsigned long start,
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unsigned long end)
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{
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if (vma->vm_mm == current->mm)
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__flush_cache_030();
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}
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static inline void flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr, unsigned long pfn)
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{
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if (vma->vm_mm == current->mm)
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__flush_cache_030();
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}
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/* Push the page at kernel virtual address and clear the icache */
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/* RZ: use cpush %bc instead of cpush %dc, cinv %ic */
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static inline void __flush_page_to_ram(void *vaddr)
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{
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if (CPU_IS_040_OR_060) {
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__asm__ __volatile__("nop\n\t"
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".chip 68040\n\t"
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"cpushp %%bc,(%0)\n\t"
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".chip 68k"
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: : "a" (__pa(vaddr)));
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} else {
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unsigned long _tmp;
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__asm__ __volatile__("movec %%cacr,%0\n\t"
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"orw %1,%0\n\t"
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"movec %0,%%cacr"
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: "=&d" (_tmp)
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: "di" (FLUSH_I));
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}
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}
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#define flush_dcache_page(page) __flush_page_to_ram(page_address(page))
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#define flush_dcache_mmap_lock(mapping) do { } while (0)
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#define flush_dcache_mmap_unlock(mapping) do { } while (0)
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#define flush_icache_page(vma, page) __flush_page_to_ram(page_address(page))
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#define flush_icache_user_range(vma,pg,adr,len) do { } while (0)
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#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
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do { \
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flush_cache_page(vma, vaddr, page_to_pfn(page));\
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memcpy(dst, src, len); \
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} while (0)
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#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
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do { \
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flush_cache_page(vma, vaddr, page_to_pfn(page));\
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memcpy(dst, src, len); \
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} while (0)
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extern void flush_icache_range(unsigned long address, unsigned long endaddr);
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#endif /* _M68K_CACHEFLUSH_H */
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