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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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9e32366fe5
The reset handler code is used for either UP or SMP. To make Tegra device can compile for UP. It needs to be moved to another file that is not SMP only. This is because the reset handler also be needed by CPU idle "powered-down" mode. So we also need to put the reset handler init function in non-SMP only and init them always. And currently the implementation of the reset handler to know which CPU is OK to bring up was identital with "cpu_present_mask". But the "cpu_present_mask" did not initialize yet when the reset handler init function was moved to init early function. We use the "cpu_possible_mask" to replace "cpu_present_mask". Then it can work on both UP and SMP case. Signed-off-by: Joseph Lo <josephl@nvidia.com> [swarren: dropped the move of v7_invalidate_l1() from one file to another, to avoid conflicts with Pavel's cleanup of this function, adjust Makefile so each line only contains 1 file.] Signed-off-by: Stephen Warren <swarren@nvidia.com>
90 lines
2.3 KiB
C
90 lines
2.3 KiB
C
/*
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* arch/arm/mach-tegra/reset.c
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*
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* Copyright (C) 2011,2012 NVIDIA Corporation.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/cpumask.h>
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#include <linux/bitops.h>
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#include <asm/cacheflush.h>
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#include <asm/hardware/cache-l2x0.h>
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#include "iomap.h"
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#include "irammap.h"
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#include "reset.h"
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#include "sleep.h"
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#include "fuse.h"
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#define TEGRA_IRAM_RESET_BASE (TEGRA_IRAM_BASE + \
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TEGRA_IRAM_RESET_HANDLER_OFFSET)
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static bool is_enabled;
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static void __init tegra_cpu_reset_handler_enable(void)
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{
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void __iomem *iram_base = IO_ADDRESS(TEGRA_IRAM_RESET_BASE);
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void __iomem *evp_cpu_reset =
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IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE + 0x100);
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void __iomem *sb_ctrl = IO_ADDRESS(TEGRA_SB_BASE);
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u32 reg;
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BUG_ON(is_enabled);
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BUG_ON(tegra_cpu_reset_handler_size > TEGRA_IRAM_RESET_HANDLER_SIZE);
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memcpy(iram_base, (void *)__tegra_cpu_reset_handler_start,
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tegra_cpu_reset_handler_size);
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/*
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* NOTE: This must be the one and only write to the EVP CPU reset
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* vector in the entire system.
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*/
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writel(TEGRA_IRAM_RESET_BASE + tegra_cpu_reset_handler_offset,
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evp_cpu_reset);
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wmb();
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reg = readl(evp_cpu_reset);
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/*
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* Prevent further modifications to the physical reset vector.
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* NOTE: Has no effect on chips prior to Tegra30.
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*/
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if (tegra_chip_id != TEGRA20) {
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reg = readl(sb_ctrl);
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reg |= 2;
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writel(reg, sb_ctrl);
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wmb();
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}
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is_enabled = true;
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}
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void __init tegra_cpu_reset_handler_init(void)
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{
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#ifdef CONFIG_SMP
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__tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_PRESENT] =
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*((u32 *)cpu_possible_mask);
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__tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_SECONDARY] =
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virt_to_phys((void *)tegra_secondary_startup);
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#endif
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#ifdef CONFIG_PM_SLEEP
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__tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_LP2] =
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virt_to_phys((void *)tegra_resume);
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#endif
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tegra_cpu_reset_handler_enable();
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}
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