Andrzej Hajda 849fb0de89 drm/exynos/hdmi: fix PLL for 27MHz settings ... Current settings for 27MHz and 27.027MHz do not work. Use the settings from vendor code instead. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>		2017-02-07 13:52:50 +09:00
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drm	drm/exynos/hdmi: fix PLL for 27MHz settings	2017-02-07 13:52:50 +09:00
host1x	gpu: host1x: Add locking to syncpt	2016-11-11 15:33:13 +01:00
ipu-v3	imx-drm plane update cleanup, YUV formats	2016-11-11 09:31:27 +10:00
vga	vgaarb: use valid dev pointer in vgaarb_info()	2016-11-22 16:40:35 +01:00
Makefile