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15ffef1ae6
Properties which are child node definitions need to have an explict type. Otherwise, a matching (DT) property can silently match when an error is desired. Fix this up tree-wide. Once this is fixed, the meta-schema will enforce this on any child node definitions. Cc: Chen-Yu Tsai <wens@csie.org> Cc: David Woodhouse <dwmw2@infradead.org> Cc: Brian Norris <computersforpeace@gmail.com> Cc: Marek Vasut <marek.vasut@gmail.com> Cc: Richard Weinberger <richard@nod.at> Cc: Vignesh Raghavendra <vigneshr@ti.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: linux-mtd@lists.infradead.org Cc: linux-gpio@vger.kernel.org Cc: linux-stm32@st-md-mailman.stormreply.com Cc: linux-spi@vger.kernel.org Acked-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Mark Brown <broonie@kernel.org> Acked-by: Alexandre TORGUE <alexandre.torgue@st.com> Signed-off-by: Rob Herring <robh@kernel.org>
145 lines
4.4 KiB
YAML
145 lines
4.4 KiB
YAML
# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/mtd/nand-controller.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NAND Chip and NAND Controller Generic Binding
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maintainers:
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- Miquel Raynal <miquel.raynal@bootlin.com>
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- Richard Weinberger <richard@nod.at>
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description: |
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The NAND controller should be represented with its own DT node, and
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all NAND chips attached to this controller should be defined as
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children nodes of the NAND controller. This representation should be
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enforced even for simple controllers supporting only one chip.
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The ECC strength and ECC step size properties define the user
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desires in terms of correction capability of a controller. Together,
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they request the ECC engine to correct {strength} bit errors per
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{size} bytes.
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The interpretation of these parameters is implementation-defined, so
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not all implementations must support all possible
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combinations. However, implementations are encouraged to further
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specify the value(s) they support.
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properties:
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$nodename:
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pattern: "^nand-controller(@.*)?"
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"#address-cells":
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const: 1
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"#size-cells":
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const: 0
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ranges: true
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patternProperties:
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"^nand@[a-f0-9]$":
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type: object
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properties:
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reg:
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description:
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Contains the native Ready/Busy IDs.
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nand-ecc-mode:
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allOf:
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- $ref: /schemas/types.yaml#/definitions/string
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- enum: [ none, soft, hw, hw_syndrome, hw_oob_first, on-die ]
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description:
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Desired ECC engine, either hardware (most of the time
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embedded in the NAND controller) or software correction
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(Linux will handle the calculations). soft_bch is deprecated
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and should be replaced by soft and nand-ecc-algo.
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nand-ecc-algo:
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allOf:
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- $ref: /schemas/types.yaml#/definitions/string
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- enum: [ hamming, bch, rs ]
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description:
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Desired ECC algorithm.
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nand-bus-width:
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allOf:
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- $ref: /schemas/types.yaml#/definitions/uint32
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- enum: [ 8, 16 ]
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- default: 8
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description:
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Bus width to the NAND chip
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nand-on-flash-bbt:
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$ref: /schemas/types.yaml#/definitions/flag
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description:
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With this property, the OS will search the device for a Bad
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Block Table (BBT). If not found, it will create one, reserve
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a few blocks at the end of the device to store it and update
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it as the device ages. Otherwise, the out-of-band area of a
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few pages of all the blocks will be scanned at boot time to
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find Bad Block Markers (BBM). These markers will help to
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build a volatile BBT in RAM.
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nand-ecc-strength:
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allOf:
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- $ref: /schemas/types.yaml#/definitions/uint32
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- minimum: 1
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description:
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Maximum number of bits that can be corrected per ECC step.
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nand-ecc-step-size:
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allOf:
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- $ref: /schemas/types.yaml#/definitions/uint32
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- minimum: 1
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description:
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Number of data bytes covered by a single ECC step.
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nand-ecc-maximize:
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$ref: /schemas/types.yaml#/definitions/flag
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description:
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Whether or not the ECC strength should be maximized. The
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maximum ECC strength is both controller and chip
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dependent. The ECC engine has to select the ECC config
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providing the best strength and taking the OOB area size
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constraint into account. This is particularly useful when
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only the in-band area is used by the upper layers, and you
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want to make your NAND as reliable as possible.
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nand-is-boot-medium:
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$ref: /schemas/types.yaml#/definitions/flag
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description:
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Whether or not the NAND chip is a boot medium. Drivers might
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use this information to select ECC algorithms supported by
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the boot ROM or similar restrictions.
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nand-rb:
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$ref: /schemas/types.yaml#/definitions/uint32-array
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description:
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Contains the native Ready/Busy IDs.
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required:
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- reg
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required:
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- "#address-cells"
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- "#size-cells"
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examples:
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- |
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nand-controller {
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#address-cells = <1>;
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#size-cells = <0>;
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/* controller specific properties */
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nand@0 {
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reg = <0>;
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nand-ecc-mode = "soft";
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nand-ecc-algo = "bch";
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/* controller specific properties */
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};
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};
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