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This patch documents RZ/G2E (a.k.a. R8A774C0) bindings for the Clock Pulse Generator driver. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
98 lines
3.9 KiB
Plaintext
98 lines
3.9 KiB
Plaintext
* Renesas Clock Pulse Generator / Module Standby and Software Reset
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On Renesas ARM SoCs (SH/R-Mobile, R-Car, RZ), the CPG (Clock Pulse Generator)
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and MSSR (Module Standby and Software Reset) blocks are intimately connected,
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and share the same register block.
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They provide the following functionalities:
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- The CPG block generates various core clocks,
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- The MSSR block provides two functions:
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1. Module Standby, providing a Clock Domain to control the clock supply
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to individual SoC devices,
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2. Reset Control, to perform a software reset of individual SoC devices.
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Required Properties:
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- compatible: Must be one of:
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- "renesas,r7s9210-cpg-mssr" for the r7s9210 SoC (RZ/A2)
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- "renesas,r8a7743-cpg-mssr" for the r8a7743 SoC (RZ/G1M)
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- "renesas,r8a7744-cpg-mssr" for the r8a7744 SoC (RZ/G1N)
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- "renesas,r8a7745-cpg-mssr" for the r8a7745 SoC (RZ/G1E)
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- "renesas,r8a77470-cpg-mssr" for the r8a77470 SoC (RZ/G1C)
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- "renesas,r8a774a1-cpg-mssr" for the r8a774a1 SoC (RZ/G2M)
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- "renesas,r8a774c0-cpg-mssr" for the r8a774c0 SoC (RZ/G2E)
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- "renesas,r8a7790-cpg-mssr" for the r8a7790 SoC (R-Car H2)
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- "renesas,r8a7791-cpg-mssr" for the r8a7791 SoC (R-Car M2-W)
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- "renesas,r8a7792-cpg-mssr" for the r8a7792 SoC (R-Car V2H)
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- "renesas,r8a7793-cpg-mssr" for the r8a7793 SoC (R-Car M2-N)
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- "renesas,r8a7794-cpg-mssr" for the r8a7794 SoC (R-Car E2)
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- "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC (R-Car H3)
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- "renesas,r8a7796-cpg-mssr" for the r8a7796 SoC (R-Car M3-W)
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- "renesas,r8a77965-cpg-mssr" for the r8a77965 SoC (R-Car M3-N)
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- "renesas,r8a77970-cpg-mssr" for the r8a77970 SoC (R-Car V3M)
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- "renesas,r8a77980-cpg-mssr" for the r8a77980 SoC (R-Car V3H)
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- "renesas,r8a77990-cpg-mssr" for the r8a77990 SoC (R-Car E3)
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- "renesas,r8a77995-cpg-mssr" for the r8a77995 SoC (R-Car D3)
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- reg: Base address and length of the memory resource used by the CPG/MSSR
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block
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- clocks: References to external parent clocks, one entry for each entry in
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clock-names
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- clock-names: List of external parent clock names. Valid names are:
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- "extal" (r7s9210, r8a7743, r8a7744, r8a7745, r8a77470, r8a774a1,
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r8a774c0, r8a7790, r8a7791, r8a7792, r8a7793, r8a7794,
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r8a7795, r8a7796, r8a77965, r8a77970, r8a77980, r8a77990,
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r8a77995)
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- "extalr" (r8a774a1, r8a7795, r8a7796, r8a77965, r8a77970, r8a77980)
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- "usb_extal" (r8a7743, r8a7744, r8a7745, r8a77470, r8a7790, r8a7791,
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r8a7793, r8a7794)
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- #clock-cells: Must be 2
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- For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
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and a core clock reference, as defined in
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<dt-bindings/clock/*-cpg-mssr.h>.
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- For module clocks, the two clock specifier cells must be "CPG_MOD" and
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a module number, as defined in the datasheet.
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- #power-domain-cells: Must be 0
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- SoC devices that are part of the CPG/MSSR Clock Domain and can be
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power-managed through Module Standby should refer to the CPG device
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node in their "power-domains" property, as documented by the generic PM
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Domain bindings in
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Documentation/devicetree/bindings/power/power_domain.txt.
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- #reset-cells: Must be 1
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- The single reset specifier cell must be the module number, as defined
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in the datasheet.
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Examples
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--------
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- CPG device node:
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cpg: clock-controller@e6150000 {
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compatible = "renesas,r8a7795-cpg-mssr";
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reg = <0 0xe6150000 0 0x1000>;
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clocks = <&extal_clk>, <&extalr_clk>;
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clock-names = "extal", "extalr";
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#clock-cells = <2>;
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#power-domain-cells = <0>;
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#reset-cells = <1>;
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};
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- CPG/MSSR Clock Domain member device node:
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scif2: serial@e6e88000 {
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compatible = "renesas,scif-r8a7795", "renesas,scif";
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reg = <0 0xe6e88000 0 64>;
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interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 310>;
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clock-names = "fck";
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dmas = <&dmac1 0x13>, <&dmac1 0x12>;
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dma-names = "tx", "rx";
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power-domains = <&cpg>;
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resets = <&cpg 310>;
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};
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