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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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5f226ddb5b
This change adds the messaging support needed to support PTP. In the case of Tx timestamps it is necessary for the Switch Management entity to return the frames via the mailbox as the host interface cannot know which port the timestamp will be delivered to. In addition there is only one clock on the entire switch, as such the entity that has BAR 4 access is the only one who can actually update the frequency as it is the only one with access. Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com> Acked-by: Richard Cochran <richardcochran@gmail.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
66 lines
2.5 KiB
C
66 lines
2.5 KiB
C
/* Intel Ethernet Switch Host Interface Driver
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* Copyright(c) 2013 - 2014 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* The full GNU General Public License is included in this distribution in
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* the file called "COPYING".
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*
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* Contact Information:
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* e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
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* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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*/
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#ifndef _FM10K_COMMON_H_
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#define _FM10K_COMMON_H_
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#include "fm10k_type.h"
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#define FM10K_REMOVED(hw_addr) unlikely(!(hw_addr))
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/* PCI configuration read */
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u16 fm10k_read_pci_cfg_word(struct fm10k_hw *hw, u32 reg);
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/* read operations, indexed using DWORDS */
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u32 fm10k_read_reg(struct fm10k_hw *hw, int reg);
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/* write operations, indexed using DWORDS */
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#define fm10k_write_reg(hw, reg, val) \
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do { \
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u32 __iomem *hw_addr = ACCESS_ONCE((hw)->hw_addr); \
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if (!FM10K_REMOVED(hw_addr)) \
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writel((val), &hw_addr[(reg)]); \
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} while (0)
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/* Switch register write operations, index using DWORDS */
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#define fm10k_write_sw_reg(hw, reg, val) \
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do { \
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u32 __iomem *sw_addr = ACCESS_ONCE((hw)->sw_addr); \
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if (!FM10K_REMOVED(sw_addr)) \
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writel((val), &sw_addr[(reg)]); \
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} while (0)
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/* read ctrl register which has no clear on read fields as PCIe flush */
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#define fm10k_write_flush(hw) fm10k_read_reg((hw), FM10K_CTRL)
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s32 fm10k_get_bus_info_generic(struct fm10k_hw *hw);
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s32 fm10k_get_invariants_generic(struct fm10k_hw *hw);
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s32 fm10k_disable_queues_generic(struct fm10k_hw *hw, u16 q_cnt);
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s32 fm10k_start_hw_generic(struct fm10k_hw *hw);
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s32 fm10k_stop_hw_generic(struct fm10k_hw *hw);
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u32 fm10k_read_hw_stats_32b(struct fm10k_hw *hw, u32 addr,
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struct fm10k_hw_stat *stat);
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#define fm10k_update_hw_base_32b(stat, delta) ((stat)->base_l += (delta))
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void fm10k_update_hw_stats_q(struct fm10k_hw *hw, struct fm10k_hw_stats_q *q,
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u32 idx, u32 count);
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#define fm10k_unbind_hw_stats_32b(s) ((s)->base_h = 0)
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void fm10k_unbind_hw_stats_q(struct fm10k_hw_stats_q *q, u32 idx, u32 count);
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s32 fm10k_get_host_state_generic(struct fm10k_hw *hw, bool *host_ready);
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#endif /* _FM10K_COMMON_H_ */
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