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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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724c80e1d6
When writeback is enabled, the GPU shadows writes to certain registers into a buffer in memory. The driver can then read the values from the shadow rather than reading back from the register across the bus. Writeback can be disabled by setting the no_wb module param to 1. On r6xx/r7xx/evergreen, the following registers are shadowed: - CP scratch registers - CP read pointer - IH write pointer On r1xx-rr5xx, the following registers are shadowed: - CP scratch registers - CP read pointer v2: - Combine wb patches for r6xx-evergreen and r1xx-r5xx - Writeback is disabled on AGP boards since it tends to be unreliable on AGP using the gart. - Check radeon_wb_init return values properly. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
310 lines
8.3 KiB
C
310 lines
8.3 KiB
C
/*
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* Copyright 2008 Advanced Micro Devices, Inc.
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* Copyright 2008 Red Hat Inc.
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* Copyright 2009 Jerome Glisse.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Dave Airlie
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* Alex Deucher
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* Jerome Glisse
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*/
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#include "drmP.h"
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#include "radeon.h"
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#include "radeon_asic.h"
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#include "atom.h"
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#include "r520d.h"
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/* This files gather functions specifics to: r520,rv530,rv560,rv570,r580 */
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static int r520_mc_wait_for_idle(struct radeon_device *rdev)
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{
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unsigned i;
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uint32_t tmp;
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for (i = 0; i < rdev->usec_timeout; i++) {
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/* read MC_STATUS */
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tmp = RREG32_MC(R520_MC_STATUS);
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if (tmp & R520_MC_STATUS_IDLE) {
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return 0;
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}
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DRM_UDELAY(1);
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}
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return -1;
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}
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static void r520_gpu_init(struct radeon_device *rdev)
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{
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unsigned pipe_select_current, gb_pipe_select, tmp;
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rv515_vga_render_disable(rdev);
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/*
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* DST_PIPE_CONFIG 0x170C
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* GB_TILE_CONFIG 0x4018
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* GB_FIFO_SIZE 0x4024
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* GB_PIPE_SELECT 0x402C
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* GB_PIPE_SELECT2 0x4124
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* Z_PIPE_SHIFT 0
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* Z_PIPE_MASK 0x000000003
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* GB_FIFO_SIZE2 0x4128
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* SC_SFIFO_SIZE_SHIFT 0
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* SC_SFIFO_SIZE_MASK 0x000000003
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* SC_MFIFO_SIZE_SHIFT 2
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* SC_MFIFO_SIZE_MASK 0x00000000C
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* FG_SFIFO_SIZE_SHIFT 4
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* FG_SFIFO_SIZE_MASK 0x000000030
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* ZB_MFIFO_SIZE_SHIFT 6
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* ZB_MFIFO_SIZE_MASK 0x0000000C0
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* GA_ENHANCE 0x4274
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* SU_REG_DEST 0x42C8
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*/
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/* workaround for RV530 */
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if (rdev->family == CHIP_RV530) {
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WREG32(0x4128, 0xFF);
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}
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r420_pipes_init(rdev);
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gb_pipe_select = RREG32(0x402C);
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tmp = RREG32(0x170C);
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pipe_select_current = (tmp >> 2) & 3;
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tmp = (1 << pipe_select_current) |
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(((gb_pipe_select >> 8) & 0xF) << 4);
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WREG32_PLL(0x000D, tmp);
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if (r520_mc_wait_for_idle(rdev)) {
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printk(KERN_WARNING "Failed to wait MC idle while "
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"programming pipes. Bad things might happen.\n");
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}
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}
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static void r520_vram_get_type(struct radeon_device *rdev)
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{
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uint32_t tmp;
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rdev->mc.vram_width = 128;
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rdev->mc.vram_is_ddr = true;
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tmp = RREG32_MC(R520_MC_CNTL0);
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switch ((tmp & R520_MEM_NUM_CHANNELS_MASK) >> R520_MEM_NUM_CHANNELS_SHIFT) {
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case 0:
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rdev->mc.vram_width = 32;
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break;
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case 1:
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rdev->mc.vram_width = 64;
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break;
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case 2:
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rdev->mc.vram_width = 128;
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break;
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case 3:
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rdev->mc.vram_width = 256;
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break;
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default:
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rdev->mc.vram_width = 128;
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break;
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}
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if (tmp & R520_MC_CHANNEL_SIZE)
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rdev->mc.vram_width *= 2;
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}
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void r520_mc_init(struct radeon_device *rdev)
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{
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r520_vram_get_type(rdev);
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r100_vram_init_sizes(rdev);
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radeon_vram_location(rdev, &rdev->mc, 0);
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rdev->mc.gtt_base_align = 0;
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if (!(rdev->flags & RADEON_IS_AGP))
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radeon_gtt_location(rdev, &rdev->mc);
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radeon_update_bandwidth_info(rdev);
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}
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void r520_mc_program(struct radeon_device *rdev)
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{
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struct rv515_mc_save save;
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/* Stops all mc clients */
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rv515_mc_stop(rdev, &save);
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/* Wait for mc idle */
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if (r520_mc_wait_for_idle(rdev))
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dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
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/* Write VRAM size in case we are limiting it */
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WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
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/* Program MC, should be a 32bits limited address space */
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WREG32_MC(R_000004_MC_FB_LOCATION,
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S_000004_MC_FB_START(rdev->mc.vram_start >> 16) |
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S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16));
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WREG32(R_000134_HDP_FB_LOCATION,
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S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
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if (rdev->flags & RADEON_IS_AGP) {
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WREG32_MC(R_000005_MC_AGP_LOCATION,
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S_000005_MC_AGP_START(rdev->mc.gtt_start >> 16) |
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S_000005_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
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WREG32_MC(R_000006_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
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WREG32_MC(R_000007_AGP_BASE_2,
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S_000007_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base)));
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} else {
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WREG32_MC(R_000005_MC_AGP_LOCATION, 0xFFFFFFFF);
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WREG32_MC(R_000006_AGP_BASE, 0);
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WREG32_MC(R_000007_AGP_BASE_2, 0);
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}
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rv515_mc_resume(rdev, &save);
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}
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static int r520_startup(struct radeon_device *rdev)
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{
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int r;
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r520_mc_program(rdev);
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/* Resume clock */
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rv515_clock_startup(rdev);
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/* Initialize GPU configuration (# pipes, ...) */
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r520_gpu_init(rdev);
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/* Initialize GART (initialize after TTM so we can allocate
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* memory through TTM but finalize after TTM) */
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if (rdev->flags & RADEON_IS_PCIE) {
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r = rv370_pcie_gart_enable(rdev);
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if (r)
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return r;
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}
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/* allocate wb buffer */
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r = radeon_wb_init(rdev);
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if (r)
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return r;
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/* Enable IRQ */
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rs600_irq_set(rdev);
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rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
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/* 1M ring buffer */
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r = r100_cp_init(rdev, 1024 * 1024);
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if (r) {
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dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
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return r;
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}
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r = r100_ib_init(rdev);
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if (r) {
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dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
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return r;
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}
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return 0;
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}
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int r520_resume(struct radeon_device *rdev)
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{
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/* Make sur GART are not working */
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if (rdev->flags & RADEON_IS_PCIE)
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rv370_pcie_gart_disable(rdev);
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/* Resume clock before doing reset */
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rv515_clock_startup(rdev);
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/* Reset gpu before posting otherwise ATOM will enter infinite loop */
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if (radeon_asic_reset(rdev)) {
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dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
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RREG32(R_000E40_RBBM_STATUS),
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RREG32(R_0007C0_CP_STAT));
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}
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/* post */
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atom_asic_init(rdev->mode_info.atom_context);
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/* Resume clock after posting */
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rv515_clock_startup(rdev);
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/* Initialize surface registers */
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radeon_surface_init(rdev);
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return r520_startup(rdev);
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}
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int r520_init(struct radeon_device *rdev)
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{
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int r;
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/* Initialize scratch registers */
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radeon_scratch_init(rdev);
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/* Initialize surface registers */
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radeon_surface_init(rdev);
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/* restore some register to sane defaults */
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r100_restore_sanity(rdev);
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/* TODO: disable VGA need to use VGA request */
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/* BIOS*/
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if (!radeon_get_bios(rdev)) {
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if (ASIC_IS_AVIVO(rdev))
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return -EINVAL;
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}
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if (rdev->is_atom_bios) {
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r = radeon_atombios_init(rdev);
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if (r)
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return r;
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} else {
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dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n");
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return -EINVAL;
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}
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/* Reset gpu before posting otherwise ATOM will enter infinite loop */
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if (radeon_asic_reset(rdev)) {
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dev_warn(rdev->dev,
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"GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
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RREG32(R_000E40_RBBM_STATUS),
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RREG32(R_0007C0_CP_STAT));
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}
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/* check if cards are posted or not */
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if (radeon_boot_test_post_card(rdev) == false)
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return -EINVAL;
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if (!radeon_card_posted(rdev) && rdev->bios) {
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DRM_INFO("GPU not posted. posting now...\n");
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atom_asic_init(rdev->mode_info.atom_context);
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}
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/* Initialize clocks */
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radeon_get_clock_info(rdev->ddev);
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/* initialize AGP */
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if (rdev->flags & RADEON_IS_AGP) {
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r = radeon_agp_init(rdev);
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if (r) {
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radeon_agp_disable(rdev);
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}
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}
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/* initialize memory controller */
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r520_mc_init(rdev);
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rv515_debugfs(rdev);
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/* Fence driver */
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r = radeon_fence_driver_init(rdev);
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if (r)
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return r;
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r = radeon_irq_kms_init(rdev);
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if (r)
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return r;
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/* Memory manager */
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r = radeon_bo_init(rdev);
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if (r)
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return r;
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r = rv370_pcie_gart_init(rdev);
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if (r)
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return r;
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rv515_set_safe_registers(rdev);
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rdev->accel_working = true;
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r = r520_startup(rdev);
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if (r) {
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/* Somethings want wront with the accel init stop accel */
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dev_err(rdev->dev, "Disabling GPU acceleration\n");
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r100_cp_fini(rdev);
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radeon_wb_fini(rdev);
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r100_ib_fini(rdev);
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radeon_irq_kms_fini(rdev);
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rv370_pcie_gart_fini(rdev);
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radeon_agp_fini(rdev);
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rdev->accel_working = false;
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}
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return 0;
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}
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