mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2025-01-19 19:16:13 +07:00
31af04cd60
The 'arm,armv8' compatible string is only for software models. It adds little value otherwise and is inconsistently used as a fallback on some platforms. Remove it from those platforms. This fixes warnings generated by the DT schema. Reported-by: Michal Simek <michal.simek@xilinx.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Will Deacon <will.deacon@arm.com> Acked-by: Antoine Tenart <antoine.tenart@bootlin.com> Acked-by: Nishanth Menon <nm@ti.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Acked-by: Chanho Min <chanho.min@lge.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com> Acked-by: Thierry Reding <treding@nvidia.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Simon Horman <horms+renesas@verge.net.au> Acked-by: Tero Kristo <t-kristo@ti.com> Acked-by: Wei Xu <xuwei5@hisilicon.com> Acked-by: Liviu Dudau <liviu.dudau@arm.com> Acked-by: Matthias Brugger <matthias.bgg@gmail.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Scott Branden <scott.branden@broadcom.com> Acked-by: Kevin Hilman <khilman@baylibre.com> Acked-by: Chunyan Zhang <zhang.lyra@gmail.com> Acked-by: Robert Richter <rrichter@cavium.com> Acked-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com> Acked-by: Dinh Nguyen <dinguyen@kernel.org> Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
150 lines
3.6 KiB
Plaintext
150 lines
3.6 KiB
Plaintext
/*
|
|
* dtsi file for Cavium ThunderX2 CN99XX processor
|
|
*
|
|
* Copyright (c) 2017 Cavium Inc.
|
|
* Copyright (c) 2013-2016 Broadcom
|
|
* Author: Zi Shen Lim <zlim@broadcom.com>
|
|
*
|
|
* This program is free software; you can redistribute it and/or
|
|
* modify it under the terms of the GNU General Public License as
|
|
* published by the Free Software Foundation; either version 2 of
|
|
* the License, or (at your option) any later version.
|
|
*/
|
|
|
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
|
|
|
/ {
|
|
model = "Cavium ThunderX2 CN99XX";
|
|
compatible = "cavium,thunderx2-cn9900", "brcm,vulcan-soc";
|
|
interrupt-parent = <&gic>;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
|
|
/* just 4 cpus now, 128 needed in full config */
|
|
cpus {
|
|
#address-cells = <0x2>;
|
|
#size-cells = <0x0>;
|
|
|
|
cpu@0 {
|
|
device_type = "cpu";
|
|
compatible = "cavium,thunder2", "brcm,vulcan";
|
|
reg = <0x0 0x0>;
|
|
enable-method = "psci";
|
|
};
|
|
|
|
cpu@1 {
|
|
device_type = "cpu";
|
|
compatible = "cavium,thunder2", "brcm,vulcan";
|
|
reg = <0x0 0x1>;
|
|
enable-method = "psci";
|
|
};
|
|
|
|
cpu@2 {
|
|
device_type = "cpu";
|
|
compatible = "cavium,thunder2", "brcm,vulcan";
|
|
reg = <0x0 0x2>;
|
|
enable-method = "psci";
|
|
};
|
|
|
|
cpu@3 {
|
|
device_type = "cpu";
|
|
compatible = "cavium,thunder2", "brcm,vulcan";
|
|
reg = <0x0 0x3>;
|
|
enable-method = "psci";
|
|
};
|
|
};
|
|
|
|
psci {
|
|
compatible = "arm,psci-0.2";
|
|
method = "smc";
|
|
};
|
|
|
|
gic: interrupt-controller@400080000 {
|
|
compatible = "arm,gic-v3";
|
|
#interrupt-cells = <3>;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
interrupt-controller;
|
|
#redistributor-regions = <1>;
|
|
reg = <0x04 0x00080000 0x0 0x20000>, /* GICD */
|
|
<0x04 0x01000000 0x0 0x1000000>; /* GICR */
|
|
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
gicits: gic-its@40010000 {
|
|
compatible = "arm,gic-v3-its";
|
|
msi-controller;
|
|
reg = <0x04 0x00100000 0x0 0x20000>; /* GIC ITS */
|
|
};
|
|
};
|
|
|
|
timer {
|
|
compatible = "arm,armv8-timer";
|
|
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
pmu {
|
|
compatible = "brcm,vulcan-pmu", "arm,armv8-pmuv3";
|
|
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; /* PMU overflow */
|
|
};
|
|
|
|
clk125mhz: uart_clk125mhz {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <125000000>;
|
|
clock-output-names = "clk125mhz";
|
|
};
|
|
|
|
pcie@30000000 {
|
|
compatible = "pci-host-ecam-generic";
|
|
device_type = "pci";
|
|
#interrupt-cells = <1>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
|
|
/* ECAM at 0x3000_0000 - 0x4000_0000 */
|
|
reg = <0x0 0x30000000 0x0 0x10000000>;
|
|
reg-names = "PCI ECAM";
|
|
|
|
/*
|
|
* PCI ranges:
|
|
* IO no supported
|
|
* MEM 0x4000_0000 - 0x6000_0000
|
|
* MEM64 pref 0x40_0000_0000 - 0x60_0000_0000
|
|
*/
|
|
ranges =
|
|
<0x02000000 0 0x40000000 0 0x40000000 0 0x20000000
|
|
0x43000000 0x40 0x00000000 0x40 0x00000000 0x20 0x00000000>;
|
|
bus-range = <0 0xff>;
|
|
interrupt-map-mask = <0 0 0 7>;
|
|
interrupt-map =
|
|
/* addr pin ic icaddr icintr */
|
|
<0 0 0 1 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
|
|
0 0 0 2 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
|
|
0 0 0 3 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
|
|
0 0 0 4 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
|
|
msi-parent = <&gicits>;
|
|
dma-coherent;
|
|
};
|
|
|
|
soc {
|
|
compatible = "simple-bus";
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
|
|
uart0: serial@402020000 {
|
|
compatible = "arm,pl011", "arm,primecell";
|
|
reg = <0x04 0x02020000 0x0 0x1000>;
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk125mhz>;
|
|
clock-names = "apb_pclk";
|
|
};
|
|
};
|
|
|
|
};
|