mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 11:18:45 +07:00
53e23dcb18
Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to a standard 2 #address-cells & #size-cells at top-level * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell mpic interrupt cells to support MPIC timers * Moved mdio nodes up one level instead of under tsec nodes * Reworked PCIe nodes to allow supportin IRQs for controller (errors) and moved PCI device IRQs down to virtual bridge level * Removed CPU properties setup by u-boot to match other .dts * Added localbus node, but no chipselect details at this point * Added MPIC / PCIe msi node * Dropping "fsl,mpc8548-IP..." from compatibles for standard blocks Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
307 lines
7.2 KiB
Plaintext
307 lines
7.2 KiB
Plaintext
/*
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* MPC8548 CDS Device Tree Source
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*
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* Copyright 2006, 2008 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/include/ "fsl/mpc8548si-pre.dtsi"
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/ {
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model = "MPC8548CDS";
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compatible = "MPC8548CDS", "MPC85xxCDS";
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aliases {
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ethernet0 = &enet0;
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ethernet1 = &enet1;
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ethernet2 = &enet2;
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ethernet3 = &enet3;
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serial0 = &serial0;
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serial1 = &serial1;
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pci0 = &pci0;
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pci1 = &pci1;
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pci2 = &pci2;
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};
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memory {
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device_type = "memory";
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reg = <0 0 0x0 0x8000000>; // 128M at 0x0
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};
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lbc: localbus@e0005000 {
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reg = <0 0xe0005000 0 0x1000>;
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};
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soc: soc8548@e0000000 {
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ranges = <0 0x0 0xe0000000 0x100000>;
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i2c@3000 {
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eeprom@50 {
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compatible = "atmel,24c64";
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reg = <0x50>;
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};
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eeprom@56 {
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compatible = "atmel,24c64";
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reg = <0x56>;
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};
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eeprom@57 {
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compatible = "atmel,24c64";
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reg = <0x57>;
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};
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};
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i2c@3100 {
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eeprom@50 {
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compatible = "atmel,24c64";
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reg = <0x50>;
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};
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};
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enet0: ethernet@24000 {
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tbi-handle = <&tbi0>;
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phy-handle = <&phy0>;
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};
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mdio@24520 {
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phy0: ethernet-phy@0 {
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interrupts = <5 1 0 0>;
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reg = <0x0>;
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device_type = "ethernet-phy";
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};
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phy1: ethernet-phy@1 {
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interrupts = <5 1 0 0>;
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reg = <0x1>;
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device_type = "ethernet-phy";
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};
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phy2: ethernet-phy@2 {
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interrupts = <5 1 0 0>;
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reg = <0x2>;
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device_type = "ethernet-phy";
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};
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phy3: ethernet-phy@3 {
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interrupts = <5 1 0 0>;
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reg = <0x3>;
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device_type = "ethernet-phy";
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};
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tbi0: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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enet1: ethernet@25000 {
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tbi-handle = <&tbi1>;
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phy-handle = <&phy1>;
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};
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mdio@25520 {
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tbi1: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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enet2: ethernet@26000 {
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tbi-handle = <&tbi2>;
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phy-handle = <&phy2>;
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};
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mdio@26520 {
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tbi2: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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enet3: ethernet@27000 {
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tbi-handle = <&tbi3>;
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phy-handle = <&phy3>;
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};
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mdio@27520 {
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tbi3: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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};
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pci0: pci@e0008000 {
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reg = <0 0xe0008000 0 0x1000>;
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ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x10000000
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0x1000000 0x0 0x00000000 0 0xe2000000 0x0 0x800000>;
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clock-frequency = <66666666>;
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interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
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interrupt-map = <
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/* IDSEL 0x4 (PCIX Slot 2) */
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0x2000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
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0x2000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
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0x2000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
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0x2000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
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/* IDSEL 0x5 (PCIX Slot 3) */
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0x2800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0
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0x2800 0x0 0x0 0x2 &mpic 0x2 0x1 0 0
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0x2800 0x0 0x0 0x3 &mpic 0x3 0x1 0 0
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0x2800 0x0 0x0 0x4 &mpic 0x0 0x1 0 0
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/* IDSEL 0x6 (PCIX Slot 4) */
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0x3000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
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0x3000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
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0x3000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0
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0x3000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
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/* IDSEL 0x8 (PCIX Slot 5) */
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0x4000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
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0x4000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
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0x4000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
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0x4000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
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/* IDSEL 0xC (Tsi310 bridge) */
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0x6000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
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0x6000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
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0x6000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
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0x6000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
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/* IDSEL 0x14 (Slot 2) */
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0xa000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
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0xa000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
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0xa000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
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0xa000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
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/* IDSEL 0x15 (Slot 3) */
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0xa800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0
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0xa800 0x0 0x0 0x2 &mpic 0x2 0x1 0 0
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0xa800 0x0 0x0 0x3 &mpic 0x3 0x1 0 0
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0xa800 0x0 0x0 0x4 &mpic 0x0 0x1 0 0
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/* IDSEL 0x16 (Slot 4) */
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0xb000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
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0xb000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
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0xb000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0
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0xb000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
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/* IDSEL 0x18 (Slot 5) */
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0xc000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
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0xc000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
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0xc000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
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0xc000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
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/* IDSEL 0x1C (Tsi310 bridge PCI primary) */
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0xe000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
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0xe000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
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0xe000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
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0xe000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0>;
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pci_bridge@1c {
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interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
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interrupt-map = <
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/* IDSEL 0x00 (PrPMC Site) */
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0000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
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0000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
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0000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
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0000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
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/* IDSEL 0x04 (VIA chip) */
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0x2000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
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0x2000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
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0x2000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
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0x2000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
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/* IDSEL 0x05 (8139) */
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0x2800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0
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/* IDSEL 0x06 (Slot 6) */
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0x3000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
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0x3000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
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0x3000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0
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0x3000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
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/* IDESL 0x07 (Slot 7) */
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0x3800 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
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0x3800 0x0 0x0 0x2 &mpic 0x0 0x1 0 0
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0x3800 0x0 0x0 0x3 &mpic 0x1 0x1 0 0
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0x3800 0x0 0x0 0x4 &mpic 0x2 0x1 0 0>;
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reg = <0xe000 0x0 0x0 0x0 0x0>;
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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ranges = <0x2000000 0x0 0x80000000
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0x2000000 0x0 0x80000000
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0x0 0x20000000
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0x1000000 0x0 0x0
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0x1000000 0x0 0x0
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0x0 0x80000>;
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clock-frequency = <33333333>;
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isa@4 {
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device_type = "isa";
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#interrupt-cells = <2>;
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#size-cells = <1>;
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#address-cells = <2>;
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reg = <0x2000 0x0 0x0 0x0 0x0>;
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ranges = <0x1 0x0 0x1000000 0x0 0x0 0x1000>;
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interrupt-parent = <&i8259>;
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i8259: interrupt-controller@20 {
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interrupt-controller;
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device_type = "interrupt-controller";
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reg = <0x1 0x20 0x2
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0x1 0xa0 0x2
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0x1 0x4d0 0x2>;
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#address-cells = <0>;
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#interrupt-cells = <2>;
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compatible = "chrp,iic";
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interrupts = <0 1 0 0>;
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interrupt-parent = <&mpic>;
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};
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rtc@70 {
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compatible = "pnpPNP,b00";
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reg = <0x1 0x70 0x2>;
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};
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};
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};
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};
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pci1: pci@e0009000 {
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reg = <0 0xe0009000 0 0x1000>;
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ranges = <0x2000000 0x0 0x90000000 0 0x90000000 0x0 0x10000000
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0x1000000 0x0 0x00000000 0 0xe2800000 0x0 0x800000>;
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clock-frequency = <66666666>;
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interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
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interrupt-map = <
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/* IDSEL 0x15 */
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0xa800 0x0 0x0 0x1 &mpic 0xb 0x1 0 0
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0xa800 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
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0xa800 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
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0xa800 0x0 0x0 0x4 &mpic 0x3 0x1 0 0>;
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};
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pci2: pcie@e000a000 {
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reg = <0 0xe000a000 0 0x1000>;
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ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
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0x1000000 0x0 0x00000000 0 0xe3000000 0x0 0x100000>;
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pcie@0 {
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ranges = <0x2000000 0x0 0xa0000000
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0x2000000 0x0 0xa0000000
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0x0 0x20000000
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0x1000000 0x0 0x0
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0x1000000 0x0 0x0
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0x0 0x100000>;
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};
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};
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};
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/include/ "fsl/mpc8548si-post.dtsi"
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