mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-06 00:16:39 +07:00
00085f1efa
The dma-mapping core and the implementations do not change the DMA attributes passed by pointer. Thus the pointer can point to const data. However the attributes do not have to be a bitfield. Instead unsigned long will do fine: 1. This is just simpler. Both in terms of reading the code and setting attributes. Instead of initializing local attributes on the stack and passing pointer to it to dma_set_attr(), just set the bits. 2. It brings safeness and checking for const correctness because the attributes are passed by value. Semantic patches for this change (at least most of them): virtual patch virtual context @r@ identifier f, attrs; @@ f(..., - struct dma_attrs *attrs + unsigned long attrs , ...) { ... } @@ identifier r.f; @@ f(..., - NULL + 0 ) and // Options: --all-includes virtual patch virtual context @r@ identifier f, attrs; type t; @@ t f(..., struct dma_attrs *attrs); @@ identifier r.f; @@ f(..., - NULL + 0 ) Link: http://lkml.kernel.org/r/1468399300-5399-2-git-send-email-k.kozlowski@samsung.com Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Acked-by: Vineet Gupta <vgupta@synopsys.com> Acked-by: Robin Murphy <robin.murphy@arm.com> Acked-by: Hans-Christian Noren Egtvedt <egtvedt@samfundet.no> Acked-by: Mark Salter <msalter@redhat.com> [c6x] Acked-by: Jesper Nilsson <jesper.nilsson@axis.com> [cris] Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch> [drm] Reviewed-by: Bart Van Assche <bart.vanassche@sandisk.com> Acked-by: Joerg Roedel <jroedel@suse.de> [iommu] Acked-by: Fabien Dessenne <fabien.dessenne@st.com> [bdisp] Reviewed-by: Marek Szyprowski <m.szyprowski@samsung.com> [vb2-core] Acked-by: David Vrabel <david.vrabel@citrix.com> [xen] Acked-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> [xen swiotlb] Acked-by: Joerg Roedel <jroedel@suse.de> [iommu] Acked-by: Richard Kuo <rkuo@codeaurora.org> [hexagon] Acked-by: Geert Uytterhoeven <geert@linux-m68k.org> [m68k] Acked-by: Gerald Schaefer <gerald.schaefer@de.ibm.com> [s390] Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Acked-by: Hans-Christian Noren Egtvedt <egtvedt@samfundet.no> [avr32] Acked-by: Vineet Gupta <vgupta@synopsys.com> [arc] Acked-by: Robin Murphy <robin.murphy@arm.com> [arm64 and dma-iommu] Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
777 lines
19 KiB
C
777 lines
19 KiB
C
/* iommu.c: Generic sparc64 IOMMU support.
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*
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* Copyright (C) 1999, 2007, 2008 David S. Miller (davem@davemloft.net)
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* Copyright (C) 1999, 2000 Jakub Jelinek (jakub@redhat.com)
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*/
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#include <linux/kernel.h>
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#include <linux/export.h>
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#include <linux/slab.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/dma-mapping.h>
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#include <linux/errno.h>
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#include <linux/iommu-helper.h>
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#include <linux/bitmap.h>
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#include <linux/iommu-common.h>
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#ifdef CONFIG_PCI
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#include <linux/pci.h>
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#endif
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#include <asm/iommu.h>
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#include "iommu_common.h"
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#include "kernel.h"
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#define STC_CTXMATCH_ADDR(STC, CTX) \
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((STC)->strbuf_ctxmatch_base + ((CTX) << 3))
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#define STC_FLUSHFLAG_INIT(STC) \
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(*((STC)->strbuf_flushflag) = 0UL)
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#define STC_FLUSHFLAG_SET(STC) \
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(*((STC)->strbuf_flushflag) != 0UL)
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#define iommu_read(__reg) \
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({ u64 __ret; \
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__asm__ __volatile__("ldxa [%1] %2, %0" \
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: "=r" (__ret) \
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: "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
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: "memory"); \
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__ret; \
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})
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#define iommu_write(__reg, __val) \
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__asm__ __volatile__("stxa %0, [%1] %2" \
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: /* no outputs */ \
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: "r" (__val), "r" (__reg), \
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"i" (ASI_PHYS_BYPASS_EC_E))
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/* Must be invoked under the IOMMU lock. */
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static void iommu_flushall(struct iommu_map_table *iommu_map_table)
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{
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struct iommu *iommu = container_of(iommu_map_table, struct iommu, tbl);
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if (iommu->iommu_flushinv) {
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iommu_write(iommu->iommu_flushinv, ~(u64)0);
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} else {
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unsigned long tag;
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int entry;
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tag = iommu->iommu_tags;
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for (entry = 0; entry < 16; entry++) {
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iommu_write(tag, 0);
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tag += 8;
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}
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/* Ensure completion of previous PIO writes. */
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(void) iommu_read(iommu->write_complete_reg);
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}
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}
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#define IOPTE_CONSISTENT(CTX) \
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(IOPTE_VALID | IOPTE_CACHE | \
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(((CTX) << 47) & IOPTE_CONTEXT))
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#define IOPTE_STREAMING(CTX) \
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(IOPTE_CONSISTENT(CTX) | IOPTE_STBUF)
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/* Existing mappings are never marked invalid, instead they
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* are pointed to a dummy page.
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*/
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#define IOPTE_IS_DUMMY(iommu, iopte) \
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((iopte_val(*iopte) & IOPTE_PAGE) == (iommu)->dummy_page_pa)
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static inline void iopte_make_dummy(struct iommu *iommu, iopte_t *iopte)
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{
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unsigned long val = iopte_val(*iopte);
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val &= ~IOPTE_PAGE;
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val |= iommu->dummy_page_pa;
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iopte_val(*iopte) = val;
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}
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int iommu_table_init(struct iommu *iommu, int tsbsize,
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u32 dma_offset, u32 dma_addr_mask,
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int numa_node)
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{
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unsigned long i, order, sz, num_tsb_entries;
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struct page *page;
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num_tsb_entries = tsbsize / sizeof(iopte_t);
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/* Setup initial software IOMMU state. */
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spin_lock_init(&iommu->lock);
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iommu->ctx_lowest_free = 1;
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iommu->tbl.table_map_base = dma_offset;
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iommu->dma_addr_mask = dma_addr_mask;
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/* Allocate and initialize the free area map. */
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sz = num_tsb_entries / 8;
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sz = (sz + 7UL) & ~7UL;
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iommu->tbl.map = kmalloc_node(sz, GFP_KERNEL, numa_node);
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if (!iommu->tbl.map)
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return -ENOMEM;
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memset(iommu->tbl.map, 0, sz);
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iommu_tbl_pool_init(&iommu->tbl, num_tsb_entries, IO_PAGE_SHIFT,
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(tlb_type != hypervisor ? iommu_flushall : NULL),
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false, 1, false);
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/* Allocate and initialize the dummy page which we
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* set inactive IO PTEs to point to.
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*/
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page = alloc_pages_node(numa_node, GFP_KERNEL, 0);
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if (!page) {
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printk(KERN_ERR "IOMMU: Error, gfp(dummy_page) failed.\n");
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goto out_free_map;
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}
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iommu->dummy_page = (unsigned long) page_address(page);
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memset((void *)iommu->dummy_page, 0, PAGE_SIZE);
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iommu->dummy_page_pa = (unsigned long) __pa(iommu->dummy_page);
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/* Now allocate and setup the IOMMU page table itself. */
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order = get_order(tsbsize);
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page = alloc_pages_node(numa_node, GFP_KERNEL, order);
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if (!page) {
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printk(KERN_ERR "IOMMU: Error, gfp(tsb) failed.\n");
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goto out_free_dummy_page;
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}
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iommu->page_table = (iopte_t *)page_address(page);
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for (i = 0; i < num_tsb_entries; i++)
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iopte_make_dummy(iommu, &iommu->page_table[i]);
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return 0;
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out_free_dummy_page:
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free_page(iommu->dummy_page);
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iommu->dummy_page = 0UL;
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out_free_map:
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kfree(iommu->tbl.map);
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iommu->tbl.map = NULL;
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return -ENOMEM;
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}
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static inline iopte_t *alloc_npages(struct device *dev,
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struct iommu *iommu,
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unsigned long npages)
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{
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unsigned long entry;
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entry = iommu_tbl_range_alloc(dev, &iommu->tbl, npages, NULL,
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(unsigned long)(-1), 0);
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if (unlikely(entry == IOMMU_ERROR_CODE))
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return NULL;
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return iommu->page_table + entry;
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}
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static int iommu_alloc_ctx(struct iommu *iommu)
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{
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int lowest = iommu->ctx_lowest_free;
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int n = find_next_zero_bit(iommu->ctx_bitmap, IOMMU_NUM_CTXS, lowest);
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if (unlikely(n == IOMMU_NUM_CTXS)) {
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n = find_next_zero_bit(iommu->ctx_bitmap, lowest, 1);
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if (unlikely(n == lowest)) {
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printk(KERN_WARNING "IOMMU: Ran out of contexts.\n");
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n = 0;
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}
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}
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if (n)
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__set_bit(n, iommu->ctx_bitmap);
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return n;
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}
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static inline void iommu_free_ctx(struct iommu *iommu, int ctx)
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{
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if (likely(ctx)) {
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__clear_bit(ctx, iommu->ctx_bitmap);
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if (ctx < iommu->ctx_lowest_free)
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iommu->ctx_lowest_free = ctx;
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}
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}
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static void *dma_4u_alloc_coherent(struct device *dev, size_t size,
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dma_addr_t *dma_addrp, gfp_t gfp,
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unsigned long attrs)
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{
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unsigned long order, first_page;
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struct iommu *iommu;
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struct page *page;
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int npages, nid;
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iopte_t *iopte;
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void *ret;
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size = IO_PAGE_ALIGN(size);
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order = get_order(size);
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if (order >= 10)
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return NULL;
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nid = dev->archdata.numa_node;
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page = alloc_pages_node(nid, gfp, order);
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if (unlikely(!page))
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return NULL;
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first_page = (unsigned long) page_address(page);
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memset((char *)first_page, 0, PAGE_SIZE << order);
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iommu = dev->archdata.iommu;
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iopte = alloc_npages(dev, iommu, size >> IO_PAGE_SHIFT);
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if (unlikely(iopte == NULL)) {
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free_pages(first_page, order);
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return NULL;
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}
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*dma_addrp = (iommu->tbl.table_map_base +
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((iopte - iommu->page_table) << IO_PAGE_SHIFT));
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ret = (void *) first_page;
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npages = size >> IO_PAGE_SHIFT;
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first_page = __pa(first_page);
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while (npages--) {
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iopte_val(*iopte) = (IOPTE_CONSISTENT(0UL) |
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IOPTE_WRITE |
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(first_page & IOPTE_PAGE));
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iopte++;
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first_page += IO_PAGE_SIZE;
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}
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return ret;
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}
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static void dma_4u_free_coherent(struct device *dev, size_t size,
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void *cpu, dma_addr_t dvma,
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unsigned long attrs)
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{
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struct iommu *iommu;
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unsigned long order, npages;
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npages = IO_PAGE_ALIGN(size) >> IO_PAGE_SHIFT;
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iommu = dev->archdata.iommu;
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iommu_tbl_range_free(&iommu->tbl, dvma, npages, IOMMU_ERROR_CODE);
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order = get_order(size);
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if (order < 10)
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free_pages((unsigned long)cpu, order);
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}
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static dma_addr_t dma_4u_map_page(struct device *dev, struct page *page,
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unsigned long offset, size_t sz,
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enum dma_data_direction direction,
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unsigned long attrs)
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{
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struct iommu *iommu;
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struct strbuf *strbuf;
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iopte_t *base;
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unsigned long flags, npages, oaddr;
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unsigned long i, base_paddr, ctx;
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u32 bus_addr, ret;
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unsigned long iopte_protection;
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iommu = dev->archdata.iommu;
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strbuf = dev->archdata.stc;
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if (unlikely(direction == DMA_NONE))
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goto bad_no_ctx;
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oaddr = (unsigned long)(page_address(page) + offset);
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npages = IO_PAGE_ALIGN(oaddr + sz) - (oaddr & IO_PAGE_MASK);
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npages >>= IO_PAGE_SHIFT;
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base = alloc_npages(dev, iommu, npages);
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spin_lock_irqsave(&iommu->lock, flags);
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ctx = 0;
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if (iommu->iommu_ctxflush)
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ctx = iommu_alloc_ctx(iommu);
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spin_unlock_irqrestore(&iommu->lock, flags);
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if (unlikely(!base))
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goto bad;
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bus_addr = (iommu->tbl.table_map_base +
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((base - iommu->page_table) << IO_PAGE_SHIFT));
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ret = bus_addr | (oaddr & ~IO_PAGE_MASK);
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base_paddr = __pa(oaddr & IO_PAGE_MASK);
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if (strbuf->strbuf_enabled)
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iopte_protection = IOPTE_STREAMING(ctx);
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else
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iopte_protection = IOPTE_CONSISTENT(ctx);
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if (direction != DMA_TO_DEVICE)
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iopte_protection |= IOPTE_WRITE;
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for (i = 0; i < npages; i++, base++, base_paddr += IO_PAGE_SIZE)
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iopte_val(*base) = iopte_protection | base_paddr;
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return ret;
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bad:
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iommu_free_ctx(iommu, ctx);
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bad_no_ctx:
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if (printk_ratelimit())
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WARN_ON(1);
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return DMA_ERROR_CODE;
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}
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static void strbuf_flush(struct strbuf *strbuf, struct iommu *iommu,
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u32 vaddr, unsigned long ctx, unsigned long npages,
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enum dma_data_direction direction)
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{
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int limit;
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if (strbuf->strbuf_ctxflush &&
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iommu->iommu_ctxflush) {
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unsigned long matchreg, flushreg;
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u64 val;
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flushreg = strbuf->strbuf_ctxflush;
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matchreg = STC_CTXMATCH_ADDR(strbuf, ctx);
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iommu_write(flushreg, ctx);
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val = iommu_read(matchreg);
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val &= 0xffff;
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if (!val)
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goto do_flush_sync;
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while (val) {
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if (val & 0x1)
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iommu_write(flushreg, ctx);
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val >>= 1;
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}
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val = iommu_read(matchreg);
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if (unlikely(val)) {
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printk(KERN_WARNING "strbuf_flush: ctx flush "
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"timeout matchreg[%llx] ctx[%lx]\n",
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val, ctx);
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goto do_page_flush;
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}
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} else {
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unsigned long i;
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do_page_flush:
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for (i = 0; i < npages; i++, vaddr += IO_PAGE_SIZE)
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iommu_write(strbuf->strbuf_pflush, vaddr);
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}
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do_flush_sync:
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/* If the device could not have possibly put dirty data into
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* the streaming cache, no flush-flag synchronization needs
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* to be performed.
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*/
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if (direction == DMA_TO_DEVICE)
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return;
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STC_FLUSHFLAG_INIT(strbuf);
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iommu_write(strbuf->strbuf_fsync, strbuf->strbuf_flushflag_pa);
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(void) iommu_read(iommu->write_complete_reg);
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limit = 100000;
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while (!STC_FLUSHFLAG_SET(strbuf)) {
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limit--;
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if (!limit)
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break;
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udelay(1);
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rmb();
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}
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if (!limit)
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printk(KERN_WARNING "strbuf_flush: flushflag timeout "
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"vaddr[%08x] ctx[%lx] npages[%ld]\n",
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vaddr, ctx, npages);
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}
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static void dma_4u_unmap_page(struct device *dev, dma_addr_t bus_addr,
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size_t sz, enum dma_data_direction direction,
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unsigned long attrs)
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{
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struct iommu *iommu;
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struct strbuf *strbuf;
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iopte_t *base;
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unsigned long flags, npages, ctx, i;
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if (unlikely(direction == DMA_NONE)) {
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if (printk_ratelimit())
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WARN_ON(1);
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return;
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}
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iommu = dev->archdata.iommu;
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strbuf = dev->archdata.stc;
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npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK);
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npages >>= IO_PAGE_SHIFT;
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base = iommu->page_table +
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((bus_addr - iommu->tbl.table_map_base) >> IO_PAGE_SHIFT);
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bus_addr &= IO_PAGE_MASK;
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spin_lock_irqsave(&iommu->lock, flags);
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/* Record the context, if any. */
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ctx = 0;
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if (iommu->iommu_ctxflush)
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ctx = (iopte_val(*base) & IOPTE_CONTEXT) >> 47UL;
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/* Step 1: Kick data out of streaming buffers if necessary. */
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if (strbuf->strbuf_enabled)
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strbuf_flush(strbuf, iommu, bus_addr, ctx,
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npages, direction);
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/* Step 2: Clear out TSB entries. */
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for (i = 0; i < npages; i++)
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iopte_make_dummy(iommu, base + i);
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iommu_free_ctx(iommu, ctx);
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spin_unlock_irqrestore(&iommu->lock, flags);
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iommu_tbl_range_free(&iommu->tbl, bus_addr, npages, IOMMU_ERROR_CODE);
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}
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static int dma_4u_map_sg(struct device *dev, struct scatterlist *sglist,
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int nelems, enum dma_data_direction direction,
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unsigned long attrs)
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{
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struct scatterlist *s, *outs, *segstart;
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unsigned long flags, handle, prot, ctx;
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dma_addr_t dma_next = 0, dma_addr;
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unsigned int max_seg_size;
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unsigned long seg_boundary_size;
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int outcount, incount, i;
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struct strbuf *strbuf;
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struct iommu *iommu;
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unsigned long base_shift;
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|
|
BUG_ON(direction == DMA_NONE);
|
|
|
|
iommu = dev->archdata.iommu;
|
|
strbuf = dev->archdata.stc;
|
|
if (nelems == 0 || !iommu)
|
|
return 0;
|
|
|
|
spin_lock_irqsave(&iommu->lock, flags);
|
|
|
|
ctx = 0;
|
|
if (iommu->iommu_ctxflush)
|
|
ctx = iommu_alloc_ctx(iommu);
|
|
|
|
if (strbuf->strbuf_enabled)
|
|
prot = IOPTE_STREAMING(ctx);
|
|
else
|
|
prot = IOPTE_CONSISTENT(ctx);
|
|
if (direction != DMA_TO_DEVICE)
|
|
prot |= IOPTE_WRITE;
|
|
|
|
outs = s = segstart = &sglist[0];
|
|
outcount = 1;
|
|
incount = nelems;
|
|
handle = 0;
|
|
|
|
/* Init first segment length for backout at failure */
|
|
outs->dma_length = 0;
|
|
|
|
max_seg_size = dma_get_max_seg_size(dev);
|
|
seg_boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
|
|
IO_PAGE_SIZE) >> IO_PAGE_SHIFT;
|
|
base_shift = iommu->tbl.table_map_base >> IO_PAGE_SHIFT;
|
|
for_each_sg(sglist, s, nelems, i) {
|
|
unsigned long paddr, npages, entry, out_entry = 0, slen;
|
|
iopte_t *base;
|
|
|
|
slen = s->length;
|
|
/* Sanity check */
|
|
if (slen == 0) {
|
|
dma_next = 0;
|
|
continue;
|
|
}
|
|
/* Allocate iommu entries for that segment */
|
|
paddr = (unsigned long) SG_ENT_PHYS_ADDRESS(s);
|
|
npages = iommu_num_pages(paddr, slen, IO_PAGE_SIZE);
|
|
entry = iommu_tbl_range_alloc(dev, &iommu->tbl, npages,
|
|
&handle, (unsigned long)(-1), 0);
|
|
|
|
/* Handle failure */
|
|
if (unlikely(entry == IOMMU_ERROR_CODE)) {
|
|
if (printk_ratelimit())
|
|
printk(KERN_INFO "iommu_alloc failed, iommu %p paddr %lx"
|
|
" npages %lx\n", iommu, paddr, npages);
|
|
goto iommu_map_failed;
|
|
}
|
|
|
|
base = iommu->page_table + entry;
|
|
|
|
/* Convert entry to a dma_addr_t */
|
|
dma_addr = iommu->tbl.table_map_base +
|
|
(entry << IO_PAGE_SHIFT);
|
|
dma_addr |= (s->offset & ~IO_PAGE_MASK);
|
|
|
|
/* Insert into HW table */
|
|
paddr &= IO_PAGE_MASK;
|
|
while (npages--) {
|
|
iopte_val(*base) = prot | paddr;
|
|
base++;
|
|
paddr += IO_PAGE_SIZE;
|
|
}
|
|
|
|
/* If we are in an open segment, try merging */
|
|
if (segstart != s) {
|
|
/* We cannot merge if:
|
|
* - allocated dma_addr isn't contiguous to previous allocation
|
|
*/
|
|
if ((dma_addr != dma_next) ||
|
|
(outs->dma_length + s->length > max_seg_size) ||
|
|
(is_span_boundary(out_entry, base_shift,
|
|
seg_boundary_size, outs, s))) {
|
|
/* Can't merge: create a new segment */
|
|
segstart = s;
|
|
outcount++;
|
|
outs = sg_next(outs);
|
|
} else {
|
|
outs->dma_length += s->length;
|
|
}
|
|
}
|
|
|
|
if (segstart == s) {
|
|
/* This is a new segment, fill entries */
|
|
outs->dma_address = dma_addr;
|
|
outs->dma_length = slen;
|
|
out_entry = entry;
|
|
}
|
|
|
|
/* Calculate next page pointer for contiguous check */
|
|
dma_next = dma_addr + slen;
|
|
}
|
|
|
|
spin_unlock_irqrestore(&iommu->lock, flags);
|
|
|
|
if (outcount < incount) {
|
|
outs = sg_next(outs);
|
|
outs->dma_address = DMA_ERROR_CODE;
|
|
outs->dma_length = 0;
|
|
}
|
|
|
|
return outcount;
|
|
|
|
iommu_map_failed:
|
|
for_each_sg(sglist, s, nelems, i) {
|
|
if (s->dma_length != 0) {
|
|
unsigned long vaddr, npages, entry, j;
|
|
iopte_t *base;
|
|
|
|
vaddr = s->dma_address & IO_PAGE_MASK;
|
|
npages = iommu_num_pages(s->dma_address, s->dma_length,
|
|
IO_PAGE_SIZE);
|
|
|
|
entry = (vaddr - iommu->tbl.table_map_base)
|
|
>> IO_PAGE_SHIFT;
|
|
base = iommu->page_table + entry;
|
|
|
|
for (j = 0; j < npages; j++)
|
|
iopte_make_dummy(iommu, base + j);
|
|
|
|
iommu_tbl_range_free(&iommu->tbl, vaddr, npages,
|
|
IOMMU_ERROR_CODE);
|
|
|
|
s->dma_address = DMA_ERROR_CODE;
|
|
s->dma_length = 0;
|
|
}
|
|
if (s == outs)
|
|
break;
|
|
}
|
|
spin_unlock_irqrestore(&iommu->lock, flags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* If contexts are being used, they are the same in all of the mappings
|
|
* we make for a particular SG.
|
|
*/
|
|
static unsigned long fetch_sg_ctx(struct iommu *iommu, struct scatterlist *sg)
|
|
{
|
|
unsigned long ctx = 0;
|
|
|
|
if (iommu->iommu_ctxflush) {
|
|
iopte_t *base;
|
|
u32 bus_addr;
|
|
struct iommu_map_table *tbl = &iommu->tbl;
|
|
|
|
bus_addr = sg->dma_address & IO_PAGE_MASK;
|
|
base = iommu->page_table +
|
|
((bus_addr - tbl->table_map_base) >> IO_PAGE_SHIFT);
|
|
|
|
ctx = (iopte_val(*base) & IOPTE_CONTEXT) >> 47UL;
|
|
}
|
|
return ctx;
|
|
}
|
|
|
|
static void dma_4u_unmap_sg(struct device *dev, struct scatterlist *sglist,
|
|
int nelems, enum dma_data_direction direction,
|
|
unsigned long attrs)
|
|
{
|
|
unsigned long flags, ctx;
|
|
struct scatterlist *sg;
|
|
struct strbuf *strbuf;
|
|
struct iommu *iommu;
|
|
|
|
BUG_ON(direction == DMA_NONE);
|
|
|
|
iommu = dev->archdata.iommu;
|
|
strbuf = dev->archdata.stc;
|
|
|
|
ctx = fetch_sg_ctx(iommu, sglist);
|
|
|
|
spin_lock_irqsave(&iommu->lock, flags);
|
|
|
|
sg = sglist;
|
|
while (nelems--) {
|
|
dma_addr_t dma_handle = sg->dma_address;
|
|
unsigned int len = sg->dma_length;
|
|
unsigned long npages, entry;
|
|
iopte_t *base;
|
|
int i;
|
|
|
|
if (!len)
|
|
break;
|
|
npages = iommu_num_pages(dma_handle, len, IO_PAGE_SIZE);
|
|
|
|
entry = ((dma_handle - iommu->tbl.table_map_base)
|
|
>> IO_PAGE_SHIFT);
|
|
base = iommu->page_table + entry;
|
|
|
|
dma_handle &= IO_PAGE_MASK;
|
|
if (strbuf->strbuf_enabled)
|
|
strbuf_flush(strbuf, iommu, dma_handle, ctx,
|
|
npages, direction);
|
|
|
|
for (i = 0; i < npages; i++)
|
|
iopte_make_dummy(iommu, base + i);
|
|
|
|
iommu_tbl_range_free(&iommu->tbl, dma_handle, npages,
|
|
IOMMU_ERROR_CODE);
|
|
sg = sg_next(sg);
|
|
}
|
|
|
|
iommu_free_ctx(iommu, ctx);
|
|
|
|
spin_unlock_irqrestore(&iommu->lock, flags);
|
|
}
|
|
|
|
static void dma_4u_sync_single_for_cpu(struct device *dev,
|
|
dma_addr_t bus_addr, size_t sz,
|
|
enum dma_data_direction direction)
|
|
{
|
|
struct iommu *iommu;
|
|
struct strbuf *strbuf;
|
|
unsigned long flags, ctx, npages;
|
|
|
|
iommu = dev->archdata.iommu;
|
|
strbuf = dev->archdata.stc;
|
|
|
|
if (!strbuf->strbuf_enabled)
|
|
return;
|
|
|
|
spin_lock_irqsave(&iommu->lock, flags);
|
|
|
|
npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK);
|
|
npages >>= IO_PAGE_SHIFT;
|
|
bus_addr &= IO_PAGE_MASK;
|
|
|
|
/* Step 1: Record the context, if any. */
|
|
ctx = 0;
|
|
if (iommu->iommu_ctxflush &&
|
|
strbuf->strbuf_ctxflush) {
|
|
iopte_t *iopte;
|
|
struct iommu_map_table *tbl = &iommu->tbl;
|
|
|
|
iopte = iommu->page_table +
|
|
((bus_addr - tbl->table_map_base)>>IO_PAGE_SHIFT);
|
|
ctx = (iopte_val(*iopte) & IOPTE_CONTEXT) >> 47UL;
|
|
}
|
|
|
|
/* Step 2: Kick data out of streaming buffers. */
|
|
strbuf_flush(strbuf, iommu, bus_addr, ctx, npages, direction);
|
|
|
|
spin_unlock_irqrestore(&iommu->lock, flags);
|
|
}
|
|
|
|
static void dma_4u_sync_sg_for_cpu(struct device *dev,
|
|
struct scatterlist *sglist, int nelems,
|
|
enum dma_data_direction direction)
|
|
{
|
|
struct iommu *iommu;
|
|
struct strbuf *strbuf;
|
|
unsigned long flags, ctx, npages, i;
|
|
struct scatterlist *sg, *sgprv;
|
|
u32 bus_addr;
|
|
|
|
iommu = dev->archdata.iommu;
|
|
strbuf = dev->archdata.stc;
|
|
|
|
if (!strbuf->strbuf_enabled)
|
|
return;
|
|
|
|
spin_lock_irqsave(&iommu->lock, flags);
|
|
|
|
/* Step 1: Record the context, if any. */
|
|
ctx = 0;
|
|
if (iommu->iommu_ctxflush &&
|
|
strbuf->strbuf_ctxflush) {
|
|
iopte_t *iopte;
|
|
struct iommu_map_table *tbl = &iommu->tbl;
|
|
|
|
iopte = iommu->page_table + ((sglist[0].dma_address -
|
|
tbl->table_map_base) >> IO_PAGE_SHIFT);
|
|
ctx = (iopte_val(*iopte) & IOPTE_CONTEXT) >> 47UL;
|
|
}
|
|
|
|
/* Step 2: Kick data out of streaming buffers. */
|
|
bus_addr = sglist[0].dma_address & IO_PAGE_MASK;
|
|
sgprv = NULL;
|
|
for_each_sg(sglist, sg, nelems, i) {
|
|
if (sg->dma_length == 0)
|
|
break;
|
|
sgprv = sg;
|
|
}
|
|
|
|
npages = (IO_PAGE_ALIGN(sgprv->dma_address + sgprv->dma_length)
|
|
- bus_addr) >> IO_PAGE_SHIFT;
|
|
strbuf_flush(strbuf, iommu, bus_addr, ctx, npages, direction);
|
|
|
|
spin_unlock_irqrestore(&iommu->lock, flags);
|
|
}
|
|
|
|
static struct dma_map_ops sun4u_dma_ops = {
|
|
.alloc = dma_4u_alloc_coherent,
|
|
.free = dma_4u_free_coherent,
|
|
.map_page = dma_4u_map_page,
|
|
.unmap_page = dma_4u_unmap_page,
|
|
.map_sg = dma_4u_map_sg,
|
|
.unmap_sg = dma_4u_unmap_sg,
|
|
.sync_single_for_cpu = dma_4u_sync_single_for_cpu,
|
|
.sync_sg_for_cpu = dma_4u_sync_sg_for_cpu,
|
|
};
|
|
|
|
struct dma_map_ops *dma_ops = &sun4u_dma_ops;
|
|
EXPORT_SYMBOL(dma_ops);
|
|
|
|
int dma_supported(struct device *dev, u64 device_mask)
|
|
{
|
|
struct iommu *iommu = dev->archdata.iommu;
|
|
u64 dma_addr_mask = iommu->dma_addr_mask;
|
|
|
|
if (device_mask >= (1UL << 32UL))
|
|
return 0;
|
|
|
|
if ((device_mask & dma_addr_mask) == dma_addr_mask)
|
|
return 1;
|
|
|
|
#ifdef CONFIG_PCI
|
|
if (dev_is_pci(dev))
|
|
return pci64_dma_supported(to_pci_dev(dev), device_mask);
|
|
#endif
|
|
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL(dma_supported);
|