mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-04 13:26:47 +07:00
d103f4d315
Hook up the r8a7791 thermal sensor to the DTS. Signed-off-by: Magnus Damm <damm@opensource.se> Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
187 lines
4.8 KiB
Plaintext
187 lines
4.8 KiB
Plaintext
/*
|
|
* Device Tree Source for the r8a7791 SoC
|
|
*
|
|
* Copyright (C) 2013 Renesas Electronics Corporation
|
|
* Copyright (C) 2013 Renesas Solutions Corp.
|
|
*
|
|
* This file is licensed under the terms of the GNU General Public License
|
|
* version 2. This program is licensed "as is" without any warranty of any
|
|
* kind, whether express or implied.
|
|
*/
|
|
|
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
|
#include <dt-bindings/interrupt-controller/irq.h>
|
|
|
|
/ {
|
|
compatible = "renesas,r8a7791";
|
|
interrupt-parent = <&gic>;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
|
|
cpus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
cpu0: cpu@0 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a15";
|
|
reg = <0>;
|
|
clock-frequency = <1300000000>;
|
|
};
|
|
|
|
cpu1: cpu@1 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a15";
|
|
reg = <1>;
|
|
clock-frequency = <1300000000>;
|
|
};
|
|
};
|
|
|
|
gic: interrupt-controller@f1001000 {
|
|
compatible = "arm,cortex-a15-gic";
|
|
#interrupt-cells = <3>;
|
|
#address-cells = <0>;
|
|
interrupt-controller;
|
|
reg = <0 0xf1001000 0 0x1000>,
|
|
<0 0xf1002000 0 0x1000>,
|
|
<0 0xf1004000 0 0x2000>,
|
|
<0 0xf1006000 0 0x2000>;
|
|
interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
|
|
};
|
|
|
|
gpio0: gpio@ffc40000 {
|
|
compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
|
|
reg = <0 0xffc40000 0 0x50>;
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
|
|
#gpio-cells = <2>;
|
|
gpio-controller;
|
|
gpio-ranges = <&pfc 0 0 32>;
|
|
#interrupt-cells = <2>;
|
|
interrupt-controller;
|
|
};
|
|
|
|
gpio1: gpio@ffc41000 {
|
|
compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
|
|
reg = <0 0xffc41000 0 0x50>;
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
|
|
#gpio-cells = <2>;
|
|
gpio-controller;
|
|
gpio-ranges = <&pfc 0 32 32>;
|
|
#interrupt-cells = <2>;
|
|
interrupt-controller;
|
|
};
|
|
|
|
gpio2: gpio@ffc42000 {
|
|
compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
|
|
reg = <0 0xffc42000 0 0x50>;
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
|
|
#gpio-cells = <2>;
|
|
gpio-controller;
|
|
gpio-ranges = <&pfc 0 64 32>;
|
|
#interrupt-cells = <2>;
|
|
interrupt-controller;
|
|
};
|
|
|
|
gpio3: gpio@ffc43000 {
|
|
compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
|
|
reg = <0 0xffc43000 0 0x50>;
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
|
|
#gpio-cells = <2>;
|
|
gpio-controller;
|
|
gpio-ranges = <&pfc 0 96 32>;
|
|
#interrupt-cells = <2>;
|
|
interrupt-controller;
|
|
};
|
|
|
|
gpio4: gpio@ffc44000 {
|
|
compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
|
|
reg = <0 0xffc44000 0 0x50>;
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
|
|
#gpio-cells = <2>;
|
|
gpio-controller;
|
|
gpio-ranges = <&pfc 0 128 32>;
|
|
#interrupt-cells = <2>;
|
|
interrupt-controller;
|
|
};
|
|
|
|
gpio5: gpio@ffc45000 {
|
|
compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
|
|
reg = <0 0xffc45000 0 0x50>;
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
|
|
#gpio-cells = <2>;
|
|
gpio-controller;
|
|
gpio-ranges = <&pfc 0 160 32>;
|
|
#interrupt-cells = <2>;
|
|
interrupt-controller;
|
|
};
|
|
|
|
gpio6: gpio@ffc45400 {
|
|
compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
|
|
reg = <0 0xffc45400 0 0x50>;
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
|
|
#gpio-cells = <2>;
|
|
gpio-controller;
|
|
gpio-ranges = <&pfc 0 192 32>;
|
|
#interrupt-cells = <2>;
|
|
interrupt-controller;
|
|
};
|
|
|
|
gpio7: gpio@ffc45800 {
|
|
compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
|
|
reg = <0 0xffc45800 0 0x50>;
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
|
|
#gpio-cells = <2>;
|
|
gpio-controller;
|
|
gpio-ranges = <&pfc 0 224 26>;
|
|
#interrupt-cells = <2>;
|
|
interrupt-controller;
|
|
};
|
|
|
|
thermal@e61f0000 {
|
|
compatible = "renesas,thermal-r8a7791", "renesas,rcar-thermal";
|
|
reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
timer {
|
|
compatible = "arm,armv7-timer";
|
|
interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
|
|
};
|
|
|
|
irqc0: interrupt-controller@e61c0000 {
|
|
compatible = "renesas,irqc-r8a7791", "renesas,irqc";
|
|
#interrupt-cells = <2>;
|
|
interrupt-controller;
|
|
reg = <0 0xe61c0000 0 0x200>;
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 1 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 2 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 3 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 12 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 13 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 14 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 15 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 16 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 17 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
pfc: pfc@e6060000 {
|
|
compatible = "renesas,pfc-r8a7791";
|
|
reg = <0 0xe6060000 0 0x250>;
|
|
#gpio-range-cells = <3>;
|
|
};
|
|
};
|