linux_dsm_epyc7002/drivers/pci/hotplug
Lukas Wunner 8350307454 PCI: pciehp: Resume to D0 on enable/disable
pciehp's IRQ thread ensures accessibility of the port by runtime resuming
its parent to D0.  However when the slot is enabled/disabled, the port
itself needs to be in D0 because its secondary bus is accessed in:

    pciehp_check_link_status(),
    pciehp_configure_device() (both called from board_added())
and
    pciehp_unconfigure_device() (called from remove_board()).

Thus, acquire a runtime PM ref on enable/disablement of the slot.

Yinghai Lu additionally discovered that some SkyLake servers feature a
Power Controller for their PCIe hotplug ports (PCIe r3.1, sec 6.7.1.8)
which requires the port to be in D0 when invoking

    pciehp_power_on_slot() (likewise called from board_added()).

If slot power is turned on while in D3hot, link training later fails:
https://lkml.kernel.org/r/20170205073454.GA253@wunner.de

The spec is silent about such a requirement, but it seems prudent to
assume that any hotplug port with a Power Controller may need this.

The present commit holds a runtime PM ref whenever slot power is turned
on and off, but it doesn't keep the port in D0 as long as slot power is
on.  If vendors determine that's necessary, they need to amend pciehp to
acquire a runtime PM ref in pciehp_power_on_slot() and release one in
pciehp_power_off_slot().

Signed-off-by: Lukas Wunner <lukas@wunner.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Cc: Mika Westerberg <mika.westerberg@linux.intel.com>
Cc: Ashok Raj <ashok.raj@intel.com>
Cc: Keith Busch <keith.busch@intel.com>
Cc: Yinghai Lu <yinghai@kernel.org>
2018-07-31 11:09:36 -05:00
..
acpi_pcihp.c PCI: shpchp: Separate existence of SHPC and permission to use it 2018-06-26 15:38:28 -05:00
acpiphp_core.c PCI: hotplug: Demidlayer registration with the core 2018-07-23 17:04:13 -05:00
acpiphp_glue.c ACPI / hotplug / PCI: Drop unnecessary parentheses 2018-06-04 12:08:06 -05:00
acpiphp_ibm.c More ACPI updates for v4.16-rc1 2018-02-09 09:44:25 -08:00
acpiphp.h PCI: Add SPDX GPL-2.0+ to replace GPL v2 or later boilerplate 2018-01-28 15:49:06 -06:00
cpci_hotplug_core.c PCI: hotplug: Demidlayer registration with the core 2018-07-23 17:04:13 -05:00
cpci_hotplug_pci.c PCI: Add SPDX GPL-2.0+ to replace GPL v2 or later boilerplate 2018-01-28 15:49:06 -06:00
cpci_hotplug.h PCI: Add SPDX GPL-2.0+ to replace GPL v2 or later boilerplate 2018-01-28 15:49:06 -06:00
cpcihp_generic.c PCI: Add SPDX GPL-2.0+ to replace GPL v2 or later boilerplate 2018-01-28 15:49:06 -06:00
cpcihp_zt5550.c PCI: Add SPDX GPL-2.0+ to replace GPL v2 or later boilerplate 2018-01-28 15:49:06 -06:00
cpcihp_zt5550.h PCI: Add SPDX GPL-2.0+ to replace GPL v2 or later boilerplate 2018-01-28 15:49:06 -06:00
cpqphp_core.c PCI: hotplug: Demidlayer registration with the core 2018-07-23 17:04:13 -05:00
cpqphp_ctrl.c PCI: cpqphp: Fix possible NULL pointer dereference 2018-02-28 14:35:54 -06:00
cpqphp_nvram.c PCI: Add SPDX GPL-2.0+ to replace GPL v2 or later boilerplate 2018-01-28 15:49:06 -06:00
cpqphp_nvram.h PCI: Add SPDX GPL-2.0+ to replace GPL v2 or later boilerplate 2018-01-28 15:49:06 -06:00
cpqphp_pci.c Merge branch 'pci/spdx' into next 2018-02-01 11:40:07 -06:00
cpqphp_sysfs.c PCI: Add SPDX GPL-2.0+ to replace GPL v2 or later boilerplate 2018-01-28 15:49:06 -06:00
cpqphp.h PCI: Add SPDX GPL-2.0+ to replace GPL v2 or later boilerplate 2018-01-28 15:49:06 -06:00
ibmphp_core.c PCI: hotplug: Demidlayer registration with the core 2018-07-23 17:04:13 -05:00
ibmphp_ebda.c PCI: hotplug: Demidlayer registration with the core 2018-07-23 17:04:13 -05:00
ibmphp_hpc.c PCI: Add SPDX GPL-2.0+ to replace GPL v2 or later boilerplate 2018-01-28 15:49:06 -06:00
ibmphp_pci.c Merge branch 'pci/spdx' into next 2018-02-01 11:40:07 -06:00
ibmphp_res.c Merge branch 'pci/spdx' into next 2018-02-01 11:40:07 -06:00
ibmphp.h PCI: Add SPDX GPL-2.0+ to replace GPL v2 or later boilerplate 2018-01-28 15:49:06 -06:00
Kconfig PCI: shpchp: Convert SHPC to be builtin only 2018-06-02 00:18:28 -05:00
Makefile License cleanup: add SPDX GPL-2.0 license identifier to files with no license 2017-11-02 11:10:55 +01:00
pci_hotplug_core.c PCI: hotplug: Demidlayer registration with the core 2018-07-23 17:04:13 -05:00
pciehp_core.c PCI: pciehp: Obey compulsory command delay after resume 2018-07-31 11:07:59 -05:00
pciehp_ctrl.c PCI: pciehp: Resume to D0 on enable/disable 2018-07-31 11:09:36 -05:00
pciehp_hpc.c PCI: pciehp: Support interrupts sent from D3hot 2018-07-31 11:08:56 -05:00
pciehp_pci.c PCI: pciehp: Declare pciehp_unconfigure_device() void 2018-07-23 17:04:11 -05:00
pciehp.h PCI: pciehp: Support interrupts sent from D3hot 2018-07-31 11:08:56 -05:00
pnv_php.c PCI: hotplug: Demidlayer registration with the core 2018-07-23 17:04:13 -05:00
rpadlpar_core.c pci-v4.16-changes 2018-02-06 09:59:40 -08:00
rpadlpar_sysfs.c pci-v4.16-changes 2018-02-06 09:59:40 -08:00
rpadlpar.h PCI: Add SPDX GPL-2.0+ to replace GPL v2 or later boilerplate 2018-01-28 15:49:06 -06:00
rpaphp_core.c PCI: hotplug: Demidlayer registration with the core 2018-07-23 17:04:13 -05:00
rpaphp_pci.c PCI: Add SPDX GPL-2.0+ to replace GPL v2 or later boilerplate 2018-01-28 15:49:06 -06:00
rpaphp_slot.c PCI: hotplug: Demidlayer registration with the core 2018-07-23 17:04:13 -05:00
rpaphp.h pci-v4.16-changes 2018-02-06 09:59:40 -08:00
s390_pci_hpc.c PCI: hotplug: Demidlayer registration with the core 2018-07-23 17:04:13 -05:00
sgi_hotplug.c PCI: hotplug: Demidlayer registration with the core 2018-07-23 17:04:13 -05:00
shpchp_core.c PCI: hotplug: Demidlayer registration with the core 2018-07-23 17:04:13 -05:00
shpchp_ctrl.c PCI: shpchp: Fix AMD POGO identification 2018-06-04 12:07:31 -05:00
shpchp_hpc.c PCI: Add SPDX GPL-2.0+ to replace GPL v2 or later boilerplate 2018-01-28 15:49:06 -06:00
shpchp_pci.c Merge branch 'pci/spdx' into next 2018-02-01 11:40:07 -06:00
shpchp_sysfs.c PCI: Add SPDX GPL-2.0+ to replace GPL v2 or later boilerplate 2018-01-28 15:49:06 -06:00
shpchp.h PCI: shpchp: Add shpchp_is_native() 2018-06-04 12:08:06 -05:00