mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-22 19:54:40 +07:00
ebb945a94b
This is a HUGE commit, but it's not nearly as bad as it looks - any problems can be isolated to a particular chipset and engine combination. It was simply too difficult to port each one at a time, the compat layers are *already* ridiculous. Most of the changes here are simply to the glue, the process for each of the engine modules was to start with a standard skeleton and copy+paste the old code into the appropriate places, fixing up variable names etc as needed. v2: Marcin Slusarz <marcin.slusarz@gmail.com> - fix find/replace bug in license header v3: Ben Skeggs <bskeggs@redhat.com> - bump indirect pushbuf size to 8KiB, 4KiB barely enough for userspace and left no space for kernel's requirements during GEM pushbuf submission. - fix duplicate assignments noticed by clang v4: Marcin Slusarz <marcin.slusarz@gmail.com> - add sparse annotations to nv04_fifo_pause/nv04_fifo_start - use ioread32_native/iowrite32_native for fifo control registers v5: Ben Skeggs <bskeggs@redhat.com> - rebase on v3.6-rc4, modified to keep copy engine fix intact - nv10/fence: unmap fence bo before destroying - fixed fermi regression when using nvidia gr fuc - fixed typo in supported dma_mask checking Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
202 lines
4.9 KiB
C
202 lines
4.9 KiB
C
/*
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* Copyright 2012 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs <bskeggs@redhat.com>
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*/
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#include <core/object.h>
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#include <core/class.h>
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#include "nouveau_drm.h"
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#include "nouveau_dma.h"
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#include "nouveau_fence.h"
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struct nv10_fence_chan {
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struct nouveau_fence_chan base;
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};
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struct nv10_fence_priv {
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struct nouveau_fence_priv base;
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struct nouveau_bo *bo;
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spinlock_t lock;
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u32 sequence;
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};
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int
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nv10_fence_emit(struct nouveau_fence *fence)
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{
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struct nouveau_channel *chan = fence->channel;
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int ret = RING_SPACE(chan, 2);
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if (ret == 0) {
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BEGIN_NV04(chan, 0, NV10_SUBCHAN_REF_CNT, 1);
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OUT_RING (chan, fence->sequence);
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FIRE_RING (chan);
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}
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return ret;
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}
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static int
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nv10_fence_sync(struct nouveau_fence *fence,
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struct nouveau_channel *prev, struct nouveau_channel *chan)
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{
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return -ENODEV;
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}
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int
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nv17_fence_sync(struct nouveau_fence *fence,
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struct nouveau_channel *prev, struct nouveau_channel *chan)
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{
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struct nv10_fence_priv *priv = chan->drm->fence;
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u32 value;
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int ret;
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if (!mutex_trylock(&prev->cli->mutex))
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return -EBUSY;
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spin_lock(&priv->lock);
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value = priv->sequence;
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priv->sequence += 2;
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spin_unlock(&priv->lock);
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ret = RING_SPACE(prev, 5);
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if (!ret) {
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BEGIN_NV04(prev, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 4);
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OUT_RING (prev, NvSema);
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OUT_RING (prev, 0);
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OUT_RING (prev, value + 0);
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OUT_RING (prev, value + 1);
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FIRE_RING (prev);
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}
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if (!ret && !(ret = RING_SPACE(chan, 5))) {
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BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 4);
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OUT_RING (chan, NvSema);
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OUT_RING (chan, 0);
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OUT_RING (chan, value + 1);
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OUT_RING (chan, value + 2);
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FIRE_RING (chan);
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}
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mutex_unlock(&prev->cli->mutex);
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return 0;
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}
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u32
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nv10_fence_read(struct nouveau_channel *chan)
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{
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return nv_ro32(chan->object, 0x0048);
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}
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void
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nv10_fence_context_del(struct nouveau_channel *chan)
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{
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struct nv10_fence_chan *fctx = chan->fence;
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nouveau_fence_context_del(&fctx->base);
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chan->fence = NULL;
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kfree(fctx);
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}
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static int
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nv10_fence_context_new(struct nouveau_channel *chan)
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{
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struct nv10_fence_priv *priv = chan->drm->fence;
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struct nv10_fence_chan *fctx;
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int ret = 0;
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fctx = chan->fence = kzalloc(sizeof(*fctx), GFP_KERNEL);
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if (!fctx)
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return -ENOMEM;
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nouveau_fence_context_new(&fctx->base);
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if (priv->bo) {
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struct ttm_mem_reg *mem = &priv->bo->bo.mem;
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struct nouveau_object *object;
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u32 start = mem->start * PAGE_SIZE;
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u32 limit = mem->start + mem->size - 1;
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ret = nouveau_object_new(nv_object(chan->cli), chan->handle,
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NvSema, 0x0002,
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&(struct nv_dma_class) {
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.flags = NV_DMA_TARGET_VRAM |
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NV_DMA_ACCESS_RDWR,
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.start = start,
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.limit = limit,
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}, sizeof(struct nv_dma_class),
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&object);
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}
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if (ret)
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nv10_fence_context_del(chan);
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return ret;
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}
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void
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nv10_fence_destroy(struct nouveau_drm *drm)
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{
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struct nv10_fence_priv *priv = drm->fence;
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nouveau_bo_unmap(priv->bo);
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nouveau_bo_ref(NULL, &priv->bo);
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drm->fence = NULL;
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kfree(priv);
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}
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int
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nv10_fence_create(struct nouveau_drm *drm)
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{
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struct nv10_fence_priv *priv;
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int ret = 0;
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priv = drm->fence = kzalloc(sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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priv->base.dtor = nv10_fence_destroy;
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priv->base.context_new = nv10_fence_context_new;
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priv->base.context_del = nv10_fence_context_del;
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priv->base.emit = nv10_fence_emit;
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priv->base.read = nv10_fence_read;
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priv->base.sync = nv10_fence_sync;
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spin_lock_init(&priv->lock);
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if (nv_device(drm->device)->chipset >= 0x17) {
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ret = nouveau_bo_new(drm->dev, 4096, 0x1000, TTM_PL_FLAG_VRAM,
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0, 0x0000, NULL, &priv->bo);
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if (!ret) {
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ret = nouveau_bo_pin(priv->bo, TTM_PL_FLAG_VRAM);
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if (!ret)
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ret = nouveau_bo_map(priv->bo);
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if (ret)
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nouveau_bo_ref(NULL, &priv->bo);
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}
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if (ret == 0) {
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nouveau_bo_wr32(priv->bo, 0x000, 0x00000000);
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priv->base.sync = nv17_fence_sync;
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}
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}
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if (ret)
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nv10_fence_destroy(drm);
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return ret;
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}
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