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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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4b78147468
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJPw2QKAAoJEIqAPN1PVmxKfv8P/2L5d38tc3+9wYuGI1l+k7Mz
xQt2PdAx/kHQGTjLE1DSoeOD6dn4aodFbPaTcsLsU9Eo4IiJnT68b8adr/bqYHKU
Cod6NSPJMaBxLBJZxXsA7nY69Z6O5SMjXxEQsiDc24gaP0jjwaeY35KJSfMug8nF
DA6rvEpchkF8QXzBmkO2t2/uPYr1YWqDZQkauLDnLRG01JnGXFz5ajv9N5pYhiFt
QyYtheg8yEnfwnQ6AlmRtGK75jZRVmrj0kOzRjE9UL7ZwtzswWJes+RE3tlgk89m
JQ7KASRmmqLpvcVJ9fG9SlGX//yBO6OEp5Km06RTxgmt0XftBDVqBTjk1EG2tfMR
SR0NIz6gJ0twKAe6U0d+5HMYalOU45H5ha9e3vCqZ8vl9JfmM95RS+TmWbGcRIqj
04Y5x3I4zq6e9D0u+211BeuRfzkQiefwWJmdPpn0oac3u5LeYbRj/aQ85fqwJWzG
f99D9VU5xgfFHPAtL3SLFiwgd9yOiMBar6eeIva+okDyOW3KaEUzs8Y4dgDyvYcg
IU//JGK51vLVmI5kXtGCwYkgRLF/Y7WKZ8TwypT+SY6iv6tPQVvApOZljq7RC9GI
mXx2z2slA90jlg3TlEFZfxr1WqbZ3TCbonU1riLeMEtkiXUpLtmKC8gbhOqfGvvn
Nzgt+YqRJXafZdELb/S+
=Rh0r
-----END PGP SIGNATURE-----
Merge tag 'mfd-3.5-1' of git://git.kernel.org/pub/scm/linux/kernel/git/sameo/mfd-2.6
Pull MFD changes from Samuel Ortiz:
"Besides the usual cleanups, this one brings:
* Support for 5 new chipsets: Intel's ICH LPC and SCH Centerton,
ST-E's STAX211, Samsung's MAX77693 and TI's LM3533.
* Device tree support for the twl6040, tps65910, da9502 and ab8500
drivers.
* Fairly big tps56910, ab8500 and db8500 updates.
* i2c support for mc13xxx.
* Our regular update for the wm8xxx driver from Mark."
Fix up various conflicts with other trees, largely due to ab5500 removal
etc.
* tag 'mfd-3.5-1' of git://git.kernel.org/pub/scm/linux/kernel/git/sameo/mfd-2.6: (106 commits)
mfd: Fix build break of max77693 by adding REGMAP_I2C option
mfd: Fix twl6040 build failure
mfd: Fix max77693 build failure
mfd: ab8500-core should depend on MFD_DB8500_PRCMU
gpio: tps65910: dt: process gpio specific device node info
mfd: Remove the parsing of dt info for tps65910 gpio
mfd: Save device node parsed platform data for tps65910 sub devices
mfd: Add r_select to lm3533 platform data
gpio: Add Intel Centerton support to gpio-sch
mfd: Emulate active low IRQs as well as active high IRQs for wm831x
mfd: Mark two lm3533 zone registers as volatile
mfd: Fix return type of lm533 attribute is_visible
mfd: Enable Device Tree support in the ab8500-pwm driver
mfd: Enable Device Tree support in the ab8500-sysctrl driver
mfd: Add support for Device Tree to twl6040
mfd: Register the twl6040 child for the ASoC codec unconditionally
mfd: Allocate twl6040 IRQ numbers dynamically
mfd: twl6040 code cleanup in interrupt initialization part
mfd: Enable ab8500-gpadc driver for Device Tree
mfd: Prevent unassigned pointer from being used in ab8500-gpadc driver
...
317 lines
12 KiB
C
317 lines
12 KiB
C
/*
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* include/linux/mfd/asic3.h
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*
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* Compaq ASIC3 headers.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Copyright 2001 Compaq Computer Corporation.
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* Copyright 2007-2008 OpenedHand Ltd.
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*/
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#ifndef __ASIC3_H__
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#define __ASIC3_H__
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#include <linux/types.h>
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struct led_classdev;
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struct asic3_led {
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const char *name;
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const char *default_trigger;
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struct led_classdev *cdev;
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};
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struct asic3_platform_data {
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u16 *gpio_config;
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unsigned int gpio_config_num;
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unsigned int irq_base;
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unsigned int gpio_base;
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unsigned int clock_rate;
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struct asic3_led *leds;
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};
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#define ASIC3_NUM_GPIO_BANKS 4
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#define ASIC3_GPIOS_PER_BANK 16
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#define ASIC3_NUM_GPIOS 64
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#define ASIC3_NR_IRQS ASIC3_NUM_GPIOS + 6
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#define ASIC3_IRQ_LED0 64
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#define ASIC3_IRQ_LED1 65
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#define ASIC3_IRQ_LED2 66
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#define ASIC3_IRQ_SPI 67
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#define ASIC3_IRQ_SMBUS 68
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#define ASIC3_IRQ_OWM 69
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#define ASIC3_TO_GPIO(gpio) (NR_BUILTIN_GPIO + (gpio))
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#define ASIC3_GPIO_BANK_A 0
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#define ASIC3_GPIO_BANK_B 1
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#define ASIC3_GPIO_BANK_C 2
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#define ASIC3_GPIO_BANK_D 3
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#define ASIC3_GPIO(bank, gpio) \
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((ASIC3_GPIOS_PER_BANK * ASIC3_GPIO_BANK_##bank) + (gpio))
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#define ASIC3_GPIO_bit(gpio) (1 << (gpio & 0xf))
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/* All offsets below are specified with this address bus shift */
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#define ASIC3_DEFAULT_ADDR_SHIFT 2
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#define ASIC3_OFFSET(base, reg) (ASIC3_##base##_BASE + ASIC3_##base##_##reg)
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#define ASIC3_GPIO_OFFSET(base, reg) \
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(ASIC3_GPIO_##base##_BASE + ASIC3_GPIO_##reg)
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#define ASIC3_GPIO_A_BASE 0x0000
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#define ASIC3_GPIO_B_BASE 0x0100
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#define ASIC3_GPIO_C_BASE 0x0200
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#define ASIC3_GPIO_D_BASE 0x0300
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#define ASIC3_GPIO_TO_BANK(gpio) ((gpio) >> 4)
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#define ASIC3_GPIO_TO_BIT(gpio) ((gpio) - \
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(ASIC3_GPIOS_PER_BANK * ((gpio) >> 4)))
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#define ASIC3_GPIO_TO_MASK(gpio) (1 << ASIC3_GPIO_TO_BIT(gpio))
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#define ASIC3_GPIO_TO_BASE(gpio) (ASIC3_GPIO_A_BASE + (((gpio) >> 4) * 0x0100))
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#define ASIC3_BANK_TO_BASE(bank) (ASIC3_GPIO_A_BASE + ((bank) * 0x100))
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#define ASIC3_GPIO_MASK 0x00 /* R/W 0:don't mask */
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#define ASIC3_GPIO_DIRECTION 0x04 /* R/W 0:input */
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#define ASIC3_GPIO_OUT 0x08 /* R/W 0:output low */
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#define ASIC3_GPIO_TRIGGER_TYPE 0x0c /* R/W 0:level */
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#define ASIC3_GPIO_EDGE_TRIGGER 0x10 /* R/W 0:falling */
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#define ASIC3_GPIO_LEVEL_TRIGGER 0x14 /* R/W 0:low level detect */
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#define ASIC3_GPIO_SLEEP_MASK 0x18 /* R/W 0:don't mask in sleep mode */
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#define ASIC3_GPIO_SLEEP_OUT 0x1c /* R/W level 0:low in sleep mode */
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#define ASIC3_GPIO_BAT_FAULT_OUT 0x20 /* R/W level 0:low in batt_fault */
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#define ASIC3_GPIO_INT_STATUS 0x24 /* R/W 0:none, 1:detect */
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#define ASIC3_GPIO_ALT_FUNCTION 0x28 /* R/W 1:LED register control */
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#define ASIC3_GPIO_SLEEP_CONF 0x2c /*
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* R/W bit 1: autosleep
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* 0: disable gposlpout in normal mode,
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* enable gposlpout in sleep mode.
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*/
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#define ASIC3_GPIO_STATUS 0x30 /* R Pin status */
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/*
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* ASIC3 GPIO config
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*
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* Bits 0..6 gpio number
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* Bits 7..13 Alternate function
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* Bit 14 Direction
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* Bit 15 Initial value
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*
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*/
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#define ASIC3_CONFIG_GPIO_PIN(config) ((config) & 0x7f)
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#define ASIC3_CONFIG_GPIO_ALT(config) (((config) & (0x7f << 7)) >> 7)
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#define ASIC3_CONFIG_GPIO_DIR(config) ((config & (1 << 14)) >> 14)
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#define ASIC3_CONFIG_GPIO_INIT(config) ((config & (1 << 15)) >> 15)
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#define ASIC3_CONFIG_GPIO(gpio, alt, dir, init) (((gpio) & 0x7f) \
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| (((alt) & 0x7f) << 7) | (((dir) & 0x1) << 14) \
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| (((init) & 0x1) << 15))
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#define ASIC3_CONFIG_GPIO_DEFAULT(gpio, dir, init) \
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ASIC3_CONFIG_GPIO((gpio), 0, (dir), (init))
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#define ASIC3_CONFIG_GPIO_DEFAULT_OUT(gpio, init) \
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ASIC3_CONFIG_GPIO((gpio), 0, 1, (init))
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/*
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* Alternate functions
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*/
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#define ASIC3_GPIOA11_PWM0 ASIC3_CONFIG_GPIO(11, 1, 1, 0)
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#define ASIC3_GPIOA12_PWM1 ASIC3_CONFIG_GPIO(12, 1, 1, 0)
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#define ASIC3_GPIOA15_CONTROL_CX ASIC3_CONFIG_GPIO(15, 1, 1, 0)
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#define ASIC3_GPIOC0_LED0 ASIC3_CONFIG_GPIO(32, 1, 0, 0)
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#define ASIC3_GPIOC1_LED1 ASIC3_CONFIG_GPIO(33, 1, 0, 0)
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#define ASIC3_GPIOC2_LED2 ASIC3_CONFIG_GPIO(34, 1, 0, 0)
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#define ASIC3_GPIOC3_SPI_RXD ASIC3_CONFIG_GPIO(35, 1, 0, 0)
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#define ASIC3_GPIOC4_CF_nCD ASIC3_CONFIG_GPIO(36, 1, 0, 0)
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#define ASIC3_GPIOC4_SPI_TXD ASIC3_CONFIG_GPIO(36, 1, 1, 0)
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#define ASIC3_GPIOC5_SPI_CLK ASIC3_CONFIG_GPIO(37, 1, 1, 0)
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#define ASIC3_GPIOC5_nCIOW ASIC3_CONFIG_GPIO(37, 1, 1, 0)
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#define ASIC3_GPIOC6_nCIOR ASIC3_CONFIG_GPIO(38, 1, 1, 0)
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#define ASIC3_GPIOC7_nPCE_1 ASIC3_CONFIG_GPIO(39, 1, 0, 0)
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#define ASIC3_GPIOC8_nPCE_2 ASIC3_CONFIG_GPIO(40, 1, 0, 0)
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#define ASIC3_GPIOC9_nPOE ASIC3_CONFIG_GPIO(41, 1, 0, 0)
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#define ASIC3_GPIOC10_nPWE ASIC3_CONFIG_GPIO(42, 1, 0, 0)
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#define ASIC3_GPIOC11_PSKTSEL ASIC3_CONFIG_GPIO(43, 1, 0, 0)
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#define ASIC3_GPIOC12_nPREG ASIC3_CONFIG_GPIO(44, 1, 0, 0)
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#define ASIC3_GPIOC13_nPWAIT ASIC3_CONFIG_GPIO(45, 1, 1, 0)
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#define ASIC3_GPIOC14_nPIOIS16 ASIC3_CONFIG_GPIO(46, 1, 1, 0)
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#define ASIC3_GPIOC15_nPIOR ASIC3_CONFIG_GPIO(47, 1, 0, 0)
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#define ASIC3_GPIOD4_CF_nCD ASIC3_CONFIG_GPIO(52, 1, 0, 0)
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#define ASIC3_GPIOD11_nCIOIS16 ASIC3_CONFIG_GPIO(59, 1, 0, 0)
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#define ASIC3_GPIOD12_nCWAIT ASIC3_CONFIG_GPIO(60, 1, 0, 0)
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#define ASIC3_GPIOD15_nPIOW ASIC3_CONFIG_GPIO(63, 1, 0, 0)
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#define ASIC3_SPI_Base 0x0400
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#define ASIC3_SPI_Control 0x0000
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#define ASIC3_SPI_TxData 0x0004
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#define ASIC3_SPI_RxData 0x0008
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#define ASIC3_SPI_Int 0x000c
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#define ASIC3_SPI_Status 0x0010
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#define SPI_CONTROL_SPR(clk) ((clk) & 0x0f) /* Clock rate */
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#define ASIC3_PWM_0_Base 0x0500
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#define ASIC3_PWM_1_Base 0x0600
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#define ASIC3_PWM_TimeBase 0x0000
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#define ASIC3_PWM_PeriodTime 0x0004
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#define ASIC3_PWM_DutyTime 0x0008
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#define PWM_TIMEBASE_VALUE(x) ((x)&0xf) /* Low 4 bits sets time base */
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#define PWM_TIMEBASE_ENABLE (1 << 4) /* Enable clock */
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#define ASIC3_NUM_LEDS 3
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#define ASIC3_LED_0_Base 0x0700
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#define ASIC3_LED_1_Base 0x0800
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#define ASIC3_LED_2_Base 0x0900
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#define ASIC3_LED_TimeBase 0x0000 /* R/W 7 bits */
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#define ASIC3_LED_PeriodTime 0x0004 /* R/W 12 bits */
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#define ASIC3_LED_DutyTime 0x0008 /* R/W 12 bits */
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#define ASIC3_LED_AutoStopCount 0x000c /* R/W 16 bits */
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/* LED TimeBase bits - match ASIC2 */
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#define LED_TBS 0x0f /* Low 4 bits sets time base, max = 13 */
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/* Note: max = 5 on hx4700 */
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/* 0: maximum time base */
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/* 1: maximum time base / 2 */
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/* n: maximum time base / 2^n */
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#define LED_EN (1 << 4) /* LED ON/OFF 0:off, 1:on */
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#define LED_AUTOSTOP (1 << 5) /* LED ON/OFF auto stop 0:disable, 1:enable */
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#define LED_ALWAYS (1 << 6) /* LED Interrupt Mask 0:No mask, 1:mask */
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#define ASIC3_CLOCK_BASE 0x0A00
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#define ASIC3_CLOCK_CDEX 0x00
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#define ASIC3_CLOCK_SEL 0x04
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#define CLOCK_CDEX_SOURCE (1 << 0) /* 2 bits */
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#define CLOCK_CDEX_SOURCE0 (1 << 0)
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#define CLOCK_CDEX_SOURCE1 (1 << 1)
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#define CLOCK_CDEX_SPI (1 << 2)
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#define CLOCK_CDEX_OWM (1 << 3)
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#define CLOCK_CDEX_PWM0 (1 << 4)
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#define CLOCK_CDEX_PWM1 (1 << 5)
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#define CLOCK_CDEX_LED0 (1 << 6)
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#define CLOCK_CDEX_LED1 (1 << 7)
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#define CLOCK_CDEX_LED2 (1 << 8)
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/* Clocks settings: 1 for 24.576 MHz, 0 for 12.288Mhz */
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#define CLOCK_CDEX_SD_HOST (1 << 9) /* R/W: SD host clock source */
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#define CLOCK_CDEX_SD_BUS (1 << 10) /* R/W: SD bus clock source ctrl */
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#define CLOCK_CDEX_SMBUS (1 << 11)
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#define CLOCK_CDEX_CONTROL_CX (1 << 12)
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#define CLOCK_CDEX_EX0 (1 << 13) /* R/W: 32.768 kHz crystal */
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#define CLOCK_CDEX_EX1 (1 << 14) /* R/W: 24.576 MHz crystal */
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#define CLOCK_SEL_SD_HCLK_SEL (1 << 0) /* R/W: SDIO host clock select */
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#define CLOCK_SEL_SD_BCLK_SEL (1 << 1) /* R/W: SDIO bus clock select */
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/* R/W: INT clock source control (32.768 kHz) */
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#define CLOCK_SEL_CX (1 << 2)
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#define ASIC3_INTR_BASE 0x0B00
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#define ASIC3_INTR_INT_MASK 0x00 /* Interrupt mask control */
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#define ASIC3_INTR_P_INT_STAT 0x04 /* Peripheral interrupt status */
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#define ASIC3_INTR_INT_CPS 0x08 /* Interrupt timer clock pre-scale */
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#define ASIC3_INTR_INT_TBS 0x0c /* Interrupt timer set */
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#define ASIC3_INTMASK_GINTMASK (1 << 0) /* Global INTs mask 1:enable */
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#define ASIC3_INTMASK_GINTEL (1 << 1) /* 1: rising edge, 0: hi level */
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#define ASIC3_INTMASK_MASK0 (1 << 2)
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#define ASIC3_INTMASK_MASK1 (1 << 3)
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#define ASIC3_INTMASK_MASK2 (1 << 4)
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#define ASIC3_INTMASK_MASK3 (1 << 5)
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#define ASIC3_INTMASK_MASK4 (1 << 6)
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#define ASIC3_INTMASK_MASK5 (1 << 7)
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#define ASIC3_INTR_PERIPHERAL_A (1 << 0)
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#define ASIC3_INTR_PERIPHERAL_B (1 << 1)
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#define ASIC3_INTR_PERIPHERAL_C (1 << 2)
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#define ASIC3_INTR_PERIPHERAL_D (1 << 3)
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#define ASIC3_INTR_LED0 (1 << 4)
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#define ASIC3_INTR_LED1 (1 << 5)
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#define ASIC3_INTR_LED2 (1 << 6)
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#define ASIC3_INTR_SPI (1 << 7)
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#define ASIC3_INTR_SMBUS (1 << 8)
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#define ASIC3_INTR_OWM (1 << 9)
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#define ASIC3_INTR_CPS(x) ((x)&0x0f) /* 4 bits, max 14 */
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#define ASIC3_INTR_CPS_SET (1 << 4) /* Time base enable */
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/* Basic control of the SD ASIC */
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#define ASIC3_SDHWCTRL_BASE 0x0E00
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#define ASIC3_SDHWCTRL_SDCONF 0x00
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#define ASIC3_SDHWCTRL_SUSPEND (1 << 0) /* 1=suspend all SD operations */
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#define ASIC3_SDHWCTRL_CLKSEL (1 << 1) /* 1=SDICK, 0=HCLK */
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#define ASIC3_SDHWCTRL_PCLR (1 << 2) /* All registers of SDIO cleared */
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#define ASIC3_SDHWCTRL_LEVCD (1 << 3) /* SD card detection: 0:low */
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/* SD card write protection: 0=high */
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#define ASIC3_SDHWCTRL_LEVWP (1 << 4)
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#define ASIC3_SDHWCTRL_SDLED (1 << 5) /* SD card LED signal 0=disable */
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/* SD card power supply ctrl 1=enable */
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#define ASIC3_SDHWCTRL_SDPWR (1 << 6)
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#define ASIC3_EXTCF_BASE 0x1100
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#define ASIC3_EXTCF_SELECT 0x00
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#define ASIC3_EXTCF_RESET 0x04
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#define ASIC3_EXTCF_SMOD0 (1 << 0) /* slot number of mode 0 */
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#define ASIC3_EXTCF_SMOD1 (1 << 1) /* slot number of mode 1 */
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#define ASIC3_EXTCF_SMOD2 (1 << 2) /* slot number of mode 2 */
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#define ASIC3_EXTCF_OWM_EN (1 << 4) /* enable onewire module */
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#define ASIC3_EXTCF_OWM_SMB (1 << 5) /* OWM bus selection */
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#define ASIC3_EXTCF_OWM_RESET (1 << 6) /* ?? used by OWM and CF */
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#define ASIC3_EXTCF_CF0_SLEEP_MODE (1 << 7) /* CF0 sleep state */
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#define ASIC3_EXTCF_CF1_SLEEP_MODE (1 << 8) /* CF1 sleep state */
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#define ASIC3_EXTCF_CF0_PWAIT_EN (1 << 10) /* CF0 PWAIT_n control */
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#define ASIC3_EXTCF_CF1_PWAIT_EN (1 << 11) /* CF1 PWAIT_n control */
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#define ASIC3_EXTCF_CF0_BUF_EN (1 << 12) /* CF0 buffer control */
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#define ASIC3_EXTCF_CF1_BUF_EN (1 << 13) /* CF1 buffer control */
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#define ASIC3_EXTCF_SD_MEM_ENABLE (1 << 14)
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#define ASIC3_EXTCF_CF_SLEEP (1 << 15) /* CF sleep mode control */
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/*********************************************
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* The Onewire interface (DS1WM) is handled
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* by the ds1wm driver.
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*
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*********************************************/
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#define ASIC3_OWM_BASE 0xC00
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/*****************************************************************************
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* The SD configuration registers are at a completely different location
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* in memory. They are divided into three sets of registers:
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*
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* SD_CONFIG Core configuration register
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* SD_CTRL Control registers for SD operations
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* SDIO_CTRL Control registers for SDIO operations
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*
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*****************************************************************************/
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#define ASIC3_SD_CONFIG_BASE 0x0400 /* Assumes 32 bit addressing */
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#define ASIC3_SD_CONFIG_SIZE 0x0200 /* Assumes 32 bit addressing */
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#define ASIC3_SD_CTRL_BASE 0x1000
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#define ASIC3_SDIO_CTRL_BASE 0x1200
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#define ASIC3_MAP_SIZE_32BIT 0x2000
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#define ASIC3_MAP_SIZE_16BIT 0x1000
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/* Functions needed by leds-asic3 */
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struct asic3;
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extern void asic3_write_register(struct asic3 *asic, unsigned int reg, u32 val);
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extern u32 asic3_read_register(struct asic3 *asic, unsigned int reg);
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#endif /* __ASIC3_H__ */
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