mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-05 10:46:40 +07:00
6edf91da43
Signed-off-by: Yevgeny Petrilin <yevgenyp@mellanox.co.il> Signed-off-by: David S. Miller <davem@davemloft.net>
603 lines
16 KiB
C
603 lines
16 KiB
C
/*
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* Copyright (c) 2007 Mellanox Technologies. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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*/
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#ifndef _MLX4_EN_H_
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#define _MLX4_EN_H_
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#include <linux/bitops.h>
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#include <linux/compiler.h>
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#include <linux/list.h>
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#include <linux/mutex.h>
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#include <linux/netdevice.h>
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#include <linux/if_vlan.h>
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#include <linux/mlx4/device.h>
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#include <linux/mlx4/qp.h>
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#include <linux/mlx4/cq.h>
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#include <linux/mlx4/srq.h>
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#include <linux/mlx4/doorbell.h>
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#include <linux/mlx4/cmd.h>
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#include "en_port.h"
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#define DRV_NAME "mlx4_en"
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#define DRV_VERSION "2.0"
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#define DRV_RELDATE "Dec 2011"
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#define MLX4_EN_MSG_LEVEL (NETIF_MSG_LINK | NETIF_MSG_IFDOWN)
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/*
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* Device constants
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*/
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#define MLX4_EN_PAGE_SHIFT 12
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#define MLX4_EN_PAGE_SIZE (1 << MLX4_EN_PAGE_SHIFT)
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#define MAX_RX_RINGS 16
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#define MIN_RX_RINGS 4
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#define TXBB_SIZE 64
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#define HEADROOM (2048 / TXBB_SIZE + 1)
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#define STAMP_STRIDE 64
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#define STAMP_DWORDS (STAMP_STRIDE / 4)
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#define STAMP_SHIFT 31
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#define STAMP_VAL 0x7fffffff
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#define STATS_DELAY (HZ / 4)
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/* Typical TSO descriptor with 16 gather entries is 352 bytes... */
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#define MAX_DESC_SIZE 512
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#define MAX_DESC_TXBBS (MAX_DESC_SIZE / TXBB_SIZE)
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/*
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* OS related constants and tunables
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*/
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#define MLX4_EN_WATCHDOG_TIMEOUT (15 * HZ)
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#define MLX4_EN_ALLOC_ORDER 2
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#define MLX4_EN_ALLOC_SIZE (PAGE_SIZE << MLX4_EN_ALLOC_ORDER)
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#define MLX4_EN_MAX_LRO_DESCRIPTORS 32
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/* Receive fragment sizes; we use at most 4 fragments (for 9600 byte MTU
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* and 4K allocations) */
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enum {
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FRAG_SZ0 = 512 - NET_IP_ALIGN,
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FRAG_SZ1 = 1024,
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FRAG_SZ2 = 4096,
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FRAG_SZ3 = MLX4_EN_ALLOC_SIZE
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};
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#define MLX4_EN_MAX_RX_FRAGS 4
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/* Maximum ring sizes */
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#define MLX4_EN_MAX_TX_SIZE 8192
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#define MLX4_EN_MAX_RX_SIZE 8192
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/* Minimum ring size for our page-allocation sceme to work */
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#define MLX4_EN_MIN_RX_SIZE (MLX4_EN_ALLOC_SIZE / SMP_CACHE_BYTES)
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#define MLX4_EN_MIN_TX_SIZE (4096 / TXBB_SIZE)
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#define MLX4_EN_SMALL_PKT_SIZE 64
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#define MLX4_EN_NUM_TX_RINGS 8
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#define MLX4_EN_NUM_PPP_RINGS 8
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#define MAX_TX_RINGS (MLX4_EN_NUM_TX_RINGS + MLX4_EN_NUM_PPP_RINGS)
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#define MLX4_EN_DEF_TX_RING_SIZE 512
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#define MLX4_EN_DEF_RX_RING_SIZE 1024
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/* Target number of packets to coalesce with interrupt moderation */
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#define MLX4_EN_RX_COAL_TARGET 44
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#define MLX4_EN_RX_COAL_TIME 0x10
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#define MLX4_EN_TX_COAL_PKTS 5
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#define MLX4_EN_TX_COAL_TIME 0x80
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#define MLX4_EN_RX_RATE_LOW 400000
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#define MLX4_EN_RX_COAL_TIME_LOW 0
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#define MLX4_EN_RX_RATE_HIGH 450000
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#define MLX4_EN_RX_COAL_TIME_HIGH 128
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#define MLX4_EN_RX_SIZE_THRESH 1024
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#define MLX4_EN_RX_RATE_THRESH (1000000 / MLX4_EN_RX_COAL_TIME_HIGH)
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#define MLX4_EN_SAMPLE_INTERVAL 0
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#define MLX4_EN_AVG_PKT_SMALL 256
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#define MLX4_EN_AUTO_CONF 0xffff
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#define MLX4_EN_DEF_RX_PAUSE 1
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#define MLX4_EN_DEF_TX_PAUSE 1
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/* Interval between successive polls in the Tx routine when polling is used
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instead of interrupts (in per-core Tx rings) - should be power of 2 */
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#define MLX4_EN_TX_POLL_MODER 16
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#define MLX4_EN_TX_POLL_TIMEOUT (HZ / 4)
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#define ETH_LLC_SNAP_SIZE 8
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#define SMALL_PACKET_SIZE (256 - NET_IP_ALIGN)
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#define HEADER_COPY_SIZE (128 - NET_IP_ALIGN)
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#define MLX4_LOOPBACK_TEST_PAYLOAD (HEADER_COPY_SIZE - ETH_HLEN)
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#define MLX4_EN_MIN_MTU 46
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#define ETH_BCAST 0xffffffffffffULL
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#define MLX4_EN_LOOPBACK_RETRIES 5
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#define MLX4_EN_LOOPBACK_TIMEOUT 100
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#ifdef MLX4_EN_PERF_STAT
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/* Number of samples to 'average' */
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#define AVG_SIZE 128
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#define AVG_FACTOR 1024
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#define NUM_PERF_STATS NUM_PERF_COUNTERS
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#define INC_PERF_COUNTER(cnt) (++(cnt))
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#define ADD_PERF_COUNTER(cnt, add) ((cnt) += (add))
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#define AVG_PERF_COUNTER(cnt, sample) \
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((cnt) = ((cnt) * (AVG_SIZE - 1) + (sample) * AVG_FACTOR) / AVG_SIZE)
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#define GET_PERF_COUNTER(cnt) (cnt)
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#define GET_AVG_PERF_COUNTER(cnt) ((cnt) / AVG_FACTOR)
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#else
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#define NUM_PERF_STATS 0
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#define INC_PERF_COUNTER(cnt) do {} while (0)
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#define ADD_PERF_COUNTER(cnt, add) do {} while (0)
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#define AVG_PERF_COUNTER(cnt, sample) do {} while (0)
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#define GET_PERF_COUNTER(cnt) (0)
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#define GET_AVG_PERF_COUNTER(cnt) (0)
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#endif /* MLX4_EN_PERF_STAT */
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/*
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* Configurables
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*/
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enum cq_type {
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RX = 0,
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TX = 1,
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};
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/*
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* Useful macros
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*/
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#define ROUNDUP_LOG2(x) ilog2(roundup_pow_of_two(x))
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#define XNOR(x, y) (!(x) == !(y))
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#define ILLEGAL_MAC(addr) (addr == 0xffffffffffffULL || addr == 0x0)
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struct mlx4_en_tx_info {
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struct sk_buff *skb;
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u32 nr_txbb;
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u8 linear;
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u8 data_offset;
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u8 inl;
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};
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#define MLX4_EN_BIT_DESC_OWN 0x80000000
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#define CTRL_SIZE sizeof(struct mlx4_wqe_ctrl_seg)
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#define MLX4_EN_MEMTYPE_PAD 0x100
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#define DS_SIZE sizeof(struct mlx4_wqe_data_seg)
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struct mlx4_en_tx_desc {
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struct mlx4_wqe_ctrl_seg ctrl;
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union {
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struct mlx4_wqe_data_seg data; /* at least one data segment */
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struct mlx4_wqe_lso_seg lso;
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struct mlx4_wqe_inline_seg inl;
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};
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};
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#define MLX4_EN_USE_SRQ 0x01000000
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#define MLX4_EN_CX3_LOW_ID 0x1000
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#define MLX4_EN_CX3_HIGH_ID 0x1005
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struct mlx4_en_rx_alloc {
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struct page *page;
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u16 offset;
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};
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struct mlx4_en_tx_ring {
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struct mlx4_hwq_resources wqres;
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u32 size ; /* number of TXBBs */
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u32 size_mask;
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u16 stride;
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u16 cqn; /* index of port CQ associated with this ring */
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u32 prod;
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u32 cons;
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u32 buf_size;
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u32 doorbell_qpn;
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void *buf;
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u16 poll_cnt;
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int blocked;
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struct mlx4_en_tx_info *tx_info;
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u8 *bounce_buf;
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u32 last_nr_txbb;
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struct mlx4_qp qp;
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struct mlx4_qp_context context;
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int qpn;
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enum mlx4_qp_state qp_state;
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struct mlx4_srq dummy;
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unsigned long bytes;
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unsigned long packets;
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unsigned long tx_csum;
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spinlock_t comp_lock;
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struct mlx4_bf bf;
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bool bf_enabled;
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};
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struct mlx4_en_rx_desc {
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/* actual number of entries depends on rx ring stride */
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struct mlx4_wqe_data_seg data[0];
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};
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struct mlx4_en_rx_ring {
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struct mlx4_hwq_resources wqres;
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struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS];
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u32 size ; /* number of Rx descs*/
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u32 actual_size;
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u32 size_mask;
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u16 stride;
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u16 log_stride;
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u16 cqn; /* index of port CQ associated with this ring */
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u32 prod;
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u32 cons;
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u32 buf_size;
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u8 fcs_del;
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void *buf;
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void *rx_info;
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unsigned long bytes;
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unsigned long packets;
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unsigned long csum_ok;
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unsigned long csum_none;
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};
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static inline int mlx4_en_can_lro(__be16 status)
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{
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return (status & cpu_to_be16(MLX4_CQE_STATUS_IPV4 |
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MLX4_CQE_STATUS_IPV4F |
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MLX4_CQE_STATUS_IPV6 |
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MLX4_CQE_STATUS_IPV4OPT |
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MLX4_CQE_STATUS_TCP |
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MLX4_CQE_STATUS_UDP |
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MLX4_CQE_STATUS_IPOK)) ==
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cpu_to_be16(MLX4_CQE_STATUS_IPV4 |
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MLX4_CQE_STATUS_IPOK |
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MLX4_CQE_STATUS_TCP);
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}
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struct mlx4_en_cq {
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struct mlx4_cq mcq;
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struct mlx4_hwq_resources wqres;
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int ring;
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spinlock_t lock;
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struct net_device *dev;
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struct napi_struct napi;
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/* Per-core Tx cq processing support */
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struct timer_list timer;
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int size;
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int buf_size;
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unsigned vector;
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enum cq_type is_tx;
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u16 moder_time;
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u16 moder_cnt;
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struct mlx4_cqe *buf;
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#define MLX4_EN_OPCODE_ERROR 0x1e
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};
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struct mlx4_en_port_profile {
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u32 flags;
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u32 tx_ring_num;
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u32 rx_ring_num;
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u32 tx_ring_size;
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u32 rx_ring_size;
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u8 rx_pause;
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u8 rx_ppp;
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u8 tx_pause;
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u8 tx_ppp;
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};
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struct mlx4_en_profile {
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int rss_xor;
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int tcp_rss;
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int udp_rss;
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u8 rss_mask;
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u32 active_ports;
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u32 small_pkt_int;
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u8 no_reset;
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struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1];
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};
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struct mlx4_en_dev {
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struct mlx4_dev *dev;
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struct pci_dev *pdev;
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struct mutex state_lock;
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struct net_device *pndev[MLX4_MAX_PORTS + 1];
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u32 port_cnt;
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bool device_up;
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struct mlx4_en_profile profile;
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u32 LSO_support;
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struct workqueue_struct *workqueue;
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struct device *dma_device;
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void __iomem *uar_map;
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struct mlx4_uar priv_uar;
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struct mlx4_mr mr;
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u32 priv_pdn;
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spinlock_t uar_lock;
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u8 mac_removed[MLX4_MAX_PORTS + 1];
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};
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struct mlx4_en_rss_map {
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int base_qpn;
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struct mlx4_qp qps[MAX_RX_RINGS];
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enum mlx4_qp_state state[MAX_RX_RINGS];
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struct mlx4_qp indir_qp;
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enum mlx4_qp_state indir_state;
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};
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struct mlx4_en_port_state {
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int link_state;
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int link_speed;
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int transciver;
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};
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struct mlx4_en_pkt_stats {
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unsigned long broadcast;
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unsigned long rx_prio[8];
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unsigned long tx_prio[8];
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#define NUM_PKT_STATS 17
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};
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struct mlx4_en_port_stats {
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unsigned long tso_packets;
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unsigned long queue_stopped;
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unsigned long wake_queue;
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unsigned long tx_timeout;
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unsigned long rx_alloc_failed;
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unsigned long rx_chksum_good;
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unsigned long rx_chksum_none;
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unsigned long tx_chksum_offload;
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#define NUM_PORT_STATS 8
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};
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struct mlx4_en_perf_stats {
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u32 tx_poll;
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u64 tx_pktsz_avg;
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u32 inflight_avg;
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u16 tx_coal_avg;
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u16 rx_coal_avg;
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u32 napi_quota;
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#define NUM_PERF_COUNTERS 6
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};
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struct mlx4_en_frag_info {
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u16 frag_size;
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u16 frag_prefix_size;
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u16 frag_stride;
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u16 frag_align;
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u16 last_offset;
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};
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struct mlx4_en_priv {
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struct mlx4_en_dev *mdev;
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struct mlx4_en_port_profile *prof;
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struct net_device *dev;
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unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
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struct net_device_stats stats;
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struct net_device_stats ret_stats;
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struct mlx4_en_port_state port_state;
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spinlock_t stats_lock;
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unsigned long last_moder_packets[MAX_RX_RINGS];
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unsigned long last_moder_tx_packets;
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unsigned long last_moder_bytes[MAX_RX_RINGS];
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unsigned long last_moder_jiffies;
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int last_moder_time[MAX_RX_RINGS];
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u16 rx_usecs;
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u16 rx_frames;
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u16 tx_usecs;
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u16 tx_frames;
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u32 pkt_rate_low;
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u16 rx_usecs_low;
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u32 pkt_rate_high;
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u16 rx_usecs_high;
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u16 sample_interval;
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u16 adaptive_rx_coal;
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u32 msg_enable;
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u32 loopback_ok;
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u32 validate_loopback;
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struct mlx4_hwq_resources res;
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int link_state;
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int last_link_state;
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bool port_up;
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int port;
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int registered;
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int allocated;
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int stride;
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u64 mac;
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int mac_index;
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unsigned max_mtu;
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int base_qpn;
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struct mlx4_en_rss_map rss_map;
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u32 ctrl_flags;
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u32 flags;
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#define MLX4_EN_FLAG_PROMISC 0x1
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#define MLX4_EN_FLAG_MC_PROMISC 0x2
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u32 tx_ring_num;
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u32 rx_ring_num;
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u32 rx_skb_size;
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struct mlx4_en_frag_info frag_info[MLX4_EN_MAX_RX_FRAGS];
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u16 num_frags;
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u16 log_rx_info;
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struct mlx4_en_tx_ring tx_ring[MAX_TX_RINGS];
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struct mlx4_en_rx_ring rx_ring[MAX_RX_RINGS];
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struct mlx4_en_cq tx_cq[MAX_TX_RINGS];
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struct mlx4_en_cq rx_cq[MAX_RX_RINGS];
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struct work_struct mcast_task;
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struct work_struct mac_task;
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struct work_struct watchdog_task;
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struct work_struct linkstate_task;
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struct delayed_work stats_task;
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struct mlx4_en_perf_stats pstats;
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struct mlx4_en_pkt_stats pkstats;
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struct mlx4_en_port_stats port_stats;
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char *mc_addrs;
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int mc_addrs_cnt;
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struct mlx4_en_stat_out_mbox hw_stats;
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int vids[128];
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bool wol;
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};
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enum mlx4_en_wol {
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MLX4_EN_WOL_MAGIC = (1ULL << 61),
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MLX4_EN_WOL_ENABLED = (1ULL << 62),
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};
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#define MLX4_EN_WOL_DO_MODIFY (1ULL << 63)
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void mlx4_en_destroy_netdev(struct net_device *dev);
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int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
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struct mlx4_en_port_profile *prof);
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int mlx4_en_start_port(struct net_device *dev);
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void mlx4_en_stop_port(struct net_device *dev);
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void mlx4_en_free_resources(struct mlx4_en_priv *priv);
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int mlx4_en_alloc_resources(struct mlx4_en_priv *priv);
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int mlx4_en_create_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq,
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int entries, int ring, enum cq_type mode);
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void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
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int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq,
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int cq_idx);
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void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
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int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
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int mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
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void mlx4_en_poll_tx_cq(unsigned long data);
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void mlx4_en_tx_irq(struct mlx4_cq *mcq);
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u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb);
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netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev);
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|
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int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv, struct mlx4_en_tx_ring *ring,
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int qpn, u32 size, u16 stride);
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void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv, struct mlx4_en_tx_ring *ring);
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int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
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struct mlx4_en_tx_ring *ring,
|
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int cq);
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void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
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struct mlx4_en_tx_ring *ring);
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|
|
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int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
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struct mlx4_en_rx_ring *ring,
|
|
u32 size, u16 stride);
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void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
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|
struct mlx4_en_rx_ring *ring);
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int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv);
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void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
|
|
struct mlx4_en_rx_ring *ring);
|
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int mlx4_en_process_rx_cq(struct net_device *dev,
|
|
struct mlx4_en_cq *cq,
|
|
int budget);
|
|
int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget);
|
|
void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride,
|
|
int is_tx, int rss, int qpn, int cqn,
|
|
struct mlx4_qp_context *context);
|
|
void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event);
|
|
int mlx4_en_map_buffer(struct mlx4_buf *buf);
|
|
void mlx4_en_unmap_buffer(struct mlx4_buf *buf);
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|
|
|
void mlx4_en_calc_rx_buf(struct net_device *dev);
|
|
int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv);
|
|
void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv);
|
|
int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring);
|
|
void mlx4_en_rx_irq(struct mlx4_cq *mcq);
|
|
|
|
int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
|
|
int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, struct mlx4_en_priv *priv);
|
|
int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu,
|
|
u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx);
|
|
int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
|
|
u8 promisc);
|
|
|
|
int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset);
|
|
int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port);
|
|
|
|
#define MLX4_EN_NUM_SELF_TEST 5
|
|
void mlx4_en_ex_selftest(struct net_device *dev, u32 *flags, u64 *buf);
|
|
u64 mlx4_en_mac_to_u64(u8 *addr);
|
|
|
|
/*
|
|
* Globals
|
|
*/
|
|
extern const struct ethtool_ops mlx4_en_ethtool_ops;
|
|
|
|
|
|
|
|
/*
|
|
* printk / logging functions
|
|
*/
|
|
|
|
__printf(3, 4)
|
|
int en_print(const char *level, const struct mlx4_en_priv *priv,
|
|
const char *format, ...);
|
|
|
|
#define en_dbg(mlevel, priv, format, arg...) \
|
|
do { \
|
|
if (NETIF_MSG_##mlevel & priv->msg_enable) \
|
|
en_print(KERN_DEBUG, priv, format, ##arg); \
|
|
} while (0)
|
|
#define en_warn(priv, format, arg...) \
|
|
en_print(KERN_WARNING, priv, format, ##arg)
|
|
#define en_err(priv, format, arg...) \
|
|
en_print(KERN_ERR, priv, format, ##arg)
|
|
#define en_info(priv, format, arg...) \
|
|
en_print(KERN_INFO, priv, format, ## arg)
|
|
|
|
#define mlx4_err(mdev, format, arg...) \
|
|
pr_err("%s %s: " format, DRV_NAME, \
|
|
dev_name(&mdev->pdev->dev), ##arg)
|
|
#define mlx4_info(mdev, format, arg...) \
|
|
pr_info("%s %s: " format, DRV_NAME, \
|
|
dev_name(&mdev->pdev->dev), ##arg)
|
|
#define mlx4_warn(mdev, format, arg...) \
|
|
pr_warning("%s %s: " format, DRV_NAME, \
|
|
dev_name(&mdev->pdev->dev), ##arg)
|
|
|
|
#endif
|