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5b855ff3f7
Some EC implementations include a small nvram space used to store verified boot context data. This boolean property lets us indicate whether this space is available or not on a specific EC implementation. Signed-off-by: Emilio López <emilio.lopez@collabora.co.uk> Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
74 lines
2.3 KiB
Plaintext
74 lines
2.3 KiB
Plaintext
ChromeOS Embedded Controller
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Google's ChromeOS EC is a Cortex-M device which talks to the AP and
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implements various function such as keyboard and battery charging.
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The EC can be connect through various means (I2C, SPI, LPC) and the
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compatible string used depends on the interface. Each connection method has
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its own driver which connects to the top level interface-agnostic EC driver.
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Other Linux driver (such as cros-ec-keyb for the matrix keyboard) connect to
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the top-level driver.
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Required properties (I2C):
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- compatible: "google,cros-ec-i2c"
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- reg: I2C slave address
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Required properties (SPI):
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- compatible: "google,cros-ec-spi"
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- reg: SPI chip select
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Optional properties (SPI):
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- google,cros-ec-spi-pre-delay: Some implementations of the EC need a little
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time to wake up from sleep before they can receive SPI transfers at a high
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clock rate. This property specifies the delay, in usecs, between the
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assertion of the CS to the start of the first clock pulse.
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- google,cros-ec-spi-msg-delay: Some implementations of the EC require some
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additional processing time in order to accept new transactions. If the delay
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between transactions is not long enough the EC may not be able to respond
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properly to subsequent transactions and cause them to hang. This property
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specifies the delay, in usecs, introduced between transactions to account
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for the time required by the EC to get back into a state in which new data
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can be accepted.
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Required properties (LPC):
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- compatible: "google,cros-ec-lpc"
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- reg: List of (IO address, size) pairs defining the interface uses
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Optional properties (all):
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- google,has-vbc-nvram: Some implementations of the EC include a small
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nvram space used to store verified boot context data. This boolean flag
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is used to specify whether this nvram is present or not.
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Example for I2C:
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i2c@12CA0000 {
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cros-ec@1e {
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reg = <0x1e>;
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compatible = "google,cros-ec-i2c";
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interrupts = <14 0>;
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interrupt-parent = <&wakeup_eint>;
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wakeup-source;
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};
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Example for SPI:
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spi@131b0000 {
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ec@0 {
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compatible = "google,cros-ec-spi";
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reg = <0x0>;
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interrupts = <14 0>;
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interrupt-parent = <&wakeup_eint>;
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wakeup-source;
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spi-max-frequency = <5000000>;
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controller-data {
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cs-gpio = <&gpf0 3 4 3 0>;
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samsung,spi-cs;
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samsung,spi-feedback-delay = <2>;
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};
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};
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};
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Example for LPC is not supplied as it is not yet implemented.
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