Dan Williams fe9a552e71 libnvdimm, nfit: fix persistence domain reporting ... The persistence domain is a point in the platform where once writes reach that destination the platform claims it will make them persistent relative to power loss. In the ACPI NFIT this is currently communicated as 2 bits in the "NFIT - Platform Capabilities Structure". The bits comprise a hierarchy, i.e. bit0 "CPU Cache Flush to NVDIMM Durability on Power Loss Capable" implies bit1 "Memory Controller Flush to NVDIMM Durability on Power Loss Capable". Commit 96c3a23905 "libnvdimm: expose platform persistence attr..." shows the persistence domain as flags, but it's really an enumerated hierarchy. Fix this newly introduced user ABI to show the closest available persistence domain before userspace develops dependencies on seeing, or needing to develop code to tolerate, the raw NFIT flags communicated through the libnvdimm-generic region attribute. Fixes: 96c3a23905 ("libnvdimm: expose platform persistence attr...") Reviewed-by: Dave Jiang <dave.jiang@intel.com> Cc: "Rafael J. Wysocki" <rjw@rjwysocki.net> Cc: Ross Zwisler <ross.zwisler@linux.intel.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>		2018-03-21 15:12:07 -07:00
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badrange.c
blk.c
btt_devs.c
btt.c
btt.h
bus.c
claim.c
core.c
dax_devs.c
dimm_devs.c
dimm.c
e820.c
Kconfig
label.c
label.h
Makefile
namespace_devs.c
nd-core.h
nd.h
pfn_devs.c
pfn.h
pmem.c
pmem.h
region_devs.c
region.c