James Zhu d0e62855fa drm/amdgpu: add uvd enc registers in header ... Add UVD encode write/read/size/base registers definition for uvd6.3 HEVC ecoding Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-and-Tested-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2017-10-06 17:43:53 -04:00
..
bif	drm/amd/amdgpu: Introduction of SI registers (v2)	2016-11-11 10:21:07 -05:00
dce	drm/amdgpu: add DP audio support for si dce6 (v3)	2017-05-24 17:39:58 -04:00
gca	drm/amd/amdgpu: add SI defines/registers	2016-11-11 10:21:08 -05:00
gmc	drm/amdgpu: implement PRT for GFX6 v2	2017-03-29 23:52:57 -04:00
oss	drm/amd/amdgpu: add SI defines/registers	2016-11-11 10:21:08 -05:00
raven1	drm/amdgpu: add register headers for VCN 1.0	2017-05-24 17:40:48 -04:00
smu	drm/amd/powerplay: add CI asics support to smumgr (v3)	2017-09-26 13:06:57 -04:00
uvd	drm/amdgpu: add uvd enc registers in header	2017-10-06 17:43:53 -04:00
vce	drm/amd/amdgpu: Introduction of SI registers (v2)	2016-11-11 10:21:07 -05:00
vega10	drm/amdgpu: add the VCE 4.0 register headers	2017-03-29 23:54:28 -04:00