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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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958f338e96
Merge L1 Terminal Fault fixes from Thomas Gleixner:
"L1TF, aka L1 Terminal Fault, is yet another speculative hardware
engineering trainwreck. It's a hardware vulnerability which allows
unprivileged speculative access to data which is available in the
Level 1 Data Cache when the page table entry controlling the virtual
address, which is used for the access, has the Present bit cleared or
other reserved bits set.
If an instruction accesses a virtual address for which the relevant
page table entry (PTE) has the Present bit cleared or other reserved
bits set, then speculative execution ignores the invalid PTE and loads
the referenced data if it is present in the Level 1 Data Cache, as if
the page referenced by the address bits in the PTE was still present
and accessible.
While this is a purely speculative mechanism and the instruction will
raise a page fault when it is retired eventually, the pure act of
loading the data and making it available to other speculative
instructions opens up the opportunity for side channel attacks to
unprivileged malicious code, similar to the Meltdown attack.
While Meltdown breaks the user space to kernel space protection, L1TF
allows to attack any physical memory address in the system and the
attack works across all protection domains. It allows an attack of SGX
and also works from inside virtual machines because the speculation
bypasses the extended page table (EPT) protection mechanism.
The assoicated CVEs are: CVE-2018-3615, CVE-2018-3620, CVE-2018-3646
The mitigations provided by this pull request include:
- Host side protection by inverting the upper address bits of a non
present page table entry so the entry points to uncacheable memory.
- Hypervisor protection by flushing L1 Data Cache on VMENTER.
- SMT (HyperThreading) control knobs, which allow to 'turn off' SMT
by offlining the sibling CPU threads. The knobs are available on
the kernel command line and at runtime via sysfs
- Control knobs for the hypervisor mitigation, related to L1D flush
and SMT control. The knobs are available on the kernel command line
and at runtime via sysfs
- Extensive documentation about L1TF including various degrees of
mitigations.
Thanks to all people who have contributed to this in various ways -
patches, review, testing, backporting - and the fruitful, sometimes
heated, but at the end constructive discussions.
There is work in progress to provide other forms of mitigations, which
might be less horrible performance wise for a particular kind of
workloads, but this is not yet ready for consumption due to their
complexity and limitations"
* 'l1tf-final' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (75 commits)
x86/microcode: Allow late microcode loading with SMT disabled
tools headers: Synchronise x86 cpufeatures.h for L1TF additions
x86/mm/kmmio: Make the tracer robust against L1TF
x86/mm/pat: Make set_memory_np() L1TF safe
x86/speculation/l1tf: Make pmd/pud_mknotpresent() invert
x86/speculation/l1tf: Invert all not present mappings
cpu/hotplug: Fix SMT supported evaluation
KVM: VMX: Tell the nested hypervisor to skip L1D flush on vmentry
x86/speculation: Use ARCH_CAPABILITIES to skip L1D flush on vmentry
x86/speculation: Simplify sysfs report of VMX L1TF vulnerability
Documentation/l1tf: Remove Yonah processors from not vulnerable list
x86/KVM/VMX: Don't set l1tf_flush_l1d from vmx_handle_external_intr()
x86/irq: Let interrupt handlers set kvm_cpu_l1tf_flush_l1d
x86: Don't include linux/irq.h from asm/hardirq.h
x86/KVM/VMX: Introduce per-host-cpu analogue of l1tf_flush_l1d
x86/irq: Demote irq_cpustat_t::__softirq_pending to u16
x86/KVM/VMX: Move the l1tf_flush_l1d test to vmx_l1d_flush()
x86/KVM/VMX: Replace 'vmx_l1d_flush_always' with 'vmx_l1d_flush_cond'
x86/KVM/VMX: Don't set l1tf_flush_l1d to true from vmx_l1d_flush()
cpu/hotplug: detect SMT disabled by BIOS
...
125 lines
3.0 KiB
C
125 lines
3.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_X86_PGTABLE_2LEVEL_H
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#define _ASM_X86_PGTABLE_2LEVEL_H
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#define pte_ERROR(e) \
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pr_err("%s:%d: bad pte %08lx\n", __FILE__, __LINE__, (e).pte_low)
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#define pgd_ERROR(e) \
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pr_err("%s:%d: bad pgd %08lx\n", __FILE__, __LINE__, pgd_val(e))
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/*
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* Certain architectures need to do special things when PTEs
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* within a page table are directly modified. Thus, the following
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* hook is made available.
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*/
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static inline void native_set_pte(pte_t *ptep , pte_t pte)
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{
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*ptep = pte;
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}
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static inline void native_set_pmd(pmd_t *pmdp, pmd_t pmd)
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{
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#ifdef CONFIG_PAGE_TABLE_ISOLATION
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pmd.pud.p4d.pgd = pti_set_user_pgtbl(&pmdp->pud.p4d.pgd, pmd.pud.p4d.pgd);
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#endif
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*pmdp = pmd;
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}
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static inline void native_set_pud(pud_t *pudp, pud_t pud)
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{
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}
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static inline void native_set_pte_atomic(pte_t *ptep, pte_t pte)
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{
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native_set_pte(ptep, pte);
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}
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static inline void native_pmd_clear(pmd_t *pmdp)
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{
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native_set_pmd(pmdp, __pmd(0));
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}
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static inline void native_pud_clear(pud_t *pudp)
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{
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}
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static inline void native_pte_clear(struct mm_struct *mm,
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unsigned long addr, pte_t *xp)
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{
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*xp = native_make_pte(0);
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}
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#ifdef CONFIG_SMP
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static inline pte_t native_ptep_get_and_clear(pte_t *xp)
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{
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return __pte(xchg(&xp->pte_low, 0));
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}
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#else
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#define native_ptep_get_and_clear(xp) native_local_ptep_get_and_clear(xp)
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#endif
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#ifdef CONFIG_SMP
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static inline pmd_t native_pmdp_get_and_clear(pmd_t *xp)
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{
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#ifdef CONFIG_PAGE_TABLE_ISOLATION
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pti_set_user_pgtbl(&xp->pud.p4d.pgd, __pgd(0));
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#endif
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return __pmd(xchg((pmdval_t *)xp, 0));
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}
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#else
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#define native_pmdp_get_and_clear(xp) native_local_pmdp_get_and_clear(xp)
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#endif
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#ifdef CONFIG_SMP
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static inline pud_t native_pudp_get_and_clear(pud_t *xp)
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{
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#ifdef CONFIG_PAGE_TABLE_ISOLATION
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pti_set_user_pgtbl(&xp->p4d.pgd, __pgd(0));
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#endif
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return __pud(xchg((pudval_t *)xp, 0));
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}
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#else
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#define native_pudp_get_and_clear(xp) native_local_pudp_get_and_clear(xp)
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#endif
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/* Bit manipulation helper on pte/pgoff entry */
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static inline unsigned long pte_bitop(unsigned long value, unsigned int rightshift,
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unsigned long mask, unsigned int leftshift)
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{
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return ((value >> rightshift) & mask) << leftshift;
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}
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/* Encode and de-code a swap entry */
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#define SWP_TYPE_BITS 5
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#define SWP_OFFSET_SHIFT (_PAGE_BIT_PROTNONE + 1)
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#define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS)
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#define __swp_type(x) (((x).val >> (_PAGE_BIT_PRESENT + 1)) \
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& ((1U << SWP_TYPE_BITS) - 1))
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#define __swp_offset(x) ((x).val >> SWP_OFFSET_SHIFT)
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#define __swp_entry(type, offset) ((swp_entry_t) { \
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((type) << (_PAGE_BIT_PRESENT + 1)) \
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| ((offset) << SWP_OFFSET_SHIFT) })
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#define __pte_to_swp_entry(pte) ((swp_entry_t) { (pte).pte_low })
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#define __swp_entry_to_pte(x) ((pte_t) { .pte = (x).val })
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/* No inverted PFNs on 2 level page tables */
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static inline u64 protnone_mask(u64 val)
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{
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return 0;
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}
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static inline u64 flip_protnone_guard(u64 oldval, u64 val, u64 mask)
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{
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return val;
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}
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static inline bool __pte_needs_invert(u64 val)
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{
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return false;
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}
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#endif /* _ASM_X86_PGTABLE_2LEVEL_H */
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