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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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e0b35c1ab5
Suspend to RAM on Odroid XU3/XU4/HC1 family (Exynos5422) causes imprecise abort: PM: Syncing filesystems ... done. Freezing user space processes ... (elapsed 0.003 seconds) done. OOM killer disabled. Freezing remaining freezable tasks ... (elapsed 0.003 seconds) done. wake enabled for irq 139 Disabling non-boot CPUs ... IRQ51 no longer affine to CPU1 IRQ52 no longer affine to CPU2 IRQ53 no longer affine to CPU3 IRQ54 no longer affine to CPU4 IRQ55 no longer affine to CPU5 IRQ56 no longer affine to CPU6 cpu cpu4: Dropping the link to regulator.40 IRQ57 no longer affine to CPU7 Unhandled fault: external abort on non-linefetch (0x1008) at 0xf081a028 Internal error: : 1008 [#1] PREEMPT SMP ARM with last call trace in exynos_suspend_enter(). The abort is caused by writing to register in secure part of sysram. Boards booted under secure firmware (e.g. Hardkernel Odroid boards) should access non-secure sysram. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
167 lines
4.5 KiB
C
167 lines
4.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2011 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* Common Header for EXYNOS machines
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*/
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#ifndef __ARCH_ARM_MACH_EXYNOS_COMMON_H
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#define __ARCH_ARM_MACH_EXYNOS_COMMON_H
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#include <linux/platform_data/cpuidle-exynos.h>
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#define EXYNOS3250_SOC_ID 0xE3472000
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#define EXYNOS3_SOC_MASK 0xFFFFF000
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#define EXYNOS4210_CPU_ID 0x43210000
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#define EXYNOS4412_CPU_ID 0xE4412200
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#define EXYNOS4_CPU_MASK 0xFFFE0000
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#define EXYNOS5250_SOC_ID 0x43520000
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#define EXYNOS5410_SOC_ID 0xE5410000
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#define EXYNOS5420_SOC_ID 0xE5420000
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#define EXYNOS5800_SOC_ID 0xE5422000
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#define EXYNOS5_SOC_MASK 0xFFFFF000
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extern unsigned long samsung_cpu_id;
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#define IS_SAMSUNG_CPU(name, id, mask) \
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static inline int is_samsung_##name(void) \
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{ \
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return ((samsung_cpu_id & mask) == (id & mask)); \
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}
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IS_SAMSUNG_CPU(exynos3250, EXYNOS3250_SOC_ID, EXYNOS3_SOC_MASK)
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IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK)
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IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK)
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IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK)
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IS_SAMSUNG_CPU(exynos5410, EXYNOS5410_SOC_ID, EXYNOS5_SOC_MASK)
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IS_SAMSUNG_CPU(exynos5420, EXYNOS5420_SOC_ID, EXYNOS5_SOC_MASK)
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IS_SAMSUNG_CPU(exynos5800, EXYNOS5800_SOC_ID, EXYNOS5_SOC_MASK)
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#if defined(CONFIG_SOC_EXYNOS3250)
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# define soc_is_exynos3250() is_samsung_exynos3250()
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#else
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# define soc_is_exynos3250() 0
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#endif
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#if defined(CONFIG_CPU_EXYNOS4210)
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# define soc_is_exynos4210() is_samsung_exynos4210()
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#else
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# define soc_is_exynos4210() 0
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#endif
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#if defined(CONFIG_SOC_EXYNOS4412)
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# define soc_is_exynos4412() is_samsung_exynos4412()
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#else
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# define soc_is_exynos4412() 0
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#endif
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#define EXYNOS4210_REV_0 (0x0)
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#define EXYNOS4210_REV_1_0 (0x10)
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#define EXYNOS4210_REV_1_1 (0x11)
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#if defined(CONFIG_SOC_EXYNOS5250)
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# define soc_is_exynos5250() is_samsung_exynos5250()
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#else
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# define soc_is_exynos5250() 0
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#endif
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#if defined(CONFIG_SOC_EXYNOS5410)
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# define soc_is_exynos5410() is_samsung_exynos5410()
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#else
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# define soc_is_exynos5410() 0
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#endif
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#if defined(CONFIG_SOC_EXYNOS5420)
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# define soc_is_exynos5420() is_samsung_exynos5420()
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#else
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# define soc_is_exynos5420() 0
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#endif
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#if defined(CONFIG_SOC_EXYNOS5800)
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# define soc_is_exynos5800() is_samsung_exynos5800()
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#else
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# define soc_is_exynos5800() 0
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#endif
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extern u32 cp15_save_diag;
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extern u32 cp15_save_power;
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extern void __iomem *sysram_ns_base_addr;
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extern void __iomem *sysram_base_addr;
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extern void __iomem *pmu_base_addr;
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void exynos_sysram_init(void);
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enum {
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FW_DO_IDLE_SLEEP,
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FW_DO_IDLE_AFTR,
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};
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void exynos_firmware_init(void);
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/* CPU BOOT mode flag for Exynos3250 SoC bootloader */
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#define C2_STATE (1 << 3)
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/*
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* Magic values for bootloader indicating chosen low power mode.
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* See also Documentation/arm/Samsung/Bootloader-interface.txt
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*/
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#define EXYNOS_SLEEP_MAGIC 0x00000bad
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#define EXYNOS_AFTR_MAGIC 0xfcba0d10
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bool __init exynos_secure_firmware_available(void);
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void exynos_set_boot_flag(unsigned int cpu, unsigned int mode);
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void exynos_clear_boot_flag(unsigned int cpu, unsigned int mode);
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extern u32 exynos_get_eint_wake_mask(void);
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#ifdef CONFIG_PM_SLEEP
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extern void __init exynos_pm_init(void);
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#else
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static inline void exynos_pm_init(void) {}
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#endif
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extern void exynos_cpu_resume(void);
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extern void exynos_cpu_resume_ns(void);
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extern const struct smp_operations exynos_smp_ops;
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extern void exynos_cpu_power_down(int cpu);
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extern void exynos_cpu_power_up(int cpu);
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extern int exynos_cpu_power_state(int cpu);
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extern void exynos_cluster_power_down(int cluster);
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extern void exynos_cluster_power_up(int cluster);
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extern int exynos_cluster_power_state(int cluster);
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extern void exynos_cpu_save_register(void);
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extern void exynos_cpu_restore_register(void);
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extern void exynos_pm_central_suspend(void);
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extern int exynos_pm_central_resume(void);
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extern void exynos_enter_aftr(void);
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#ifdef CONFIG_SMP
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extern void exynos_scu_enable(void);
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#else
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static inline void exynos_scu_enable(void) { }
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#endif
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extern struct cpuidle_exynos_data cpuidle_coupled_exynos_data;
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extern void exynos_set_delayed_reset_assertion(bool enable);
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extern unsigned int samsung_rev(void);
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extern void exynos_core_restart(u32 core_id);
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extern int exynos_set_boot_addr(u32 core_id, unsigned long boot_addr);
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extern int exynos_get_boot_addr(u32 core_id, unsigned long *boot_addr);
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static inline void pmu_raw_writel(u32 val, u32 offset)
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{
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writel_relaxed(val, pmu_base_addr + offset);
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}
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static inline u32 pmu_raw_readl(u32 offset)
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{
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return readl_relaxed(pmu_base_addr + offset);
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}
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#endif /* __ARCH_ARM_MACH_EXYNOS_COMMON_H */
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