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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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0fc2273b9a
WaEnableStateCacheRedirectToCS context workaround configures the L3 cache
to benefit 3d workloads but media has different requirements.
Remove the workaround and whitelist the register to allow any userspace
configure the behaviour to their liking.
v2:
* Remove the workaround apart from adding the whitelist.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: kevin.ma@intel.com
Cc: xiaogang.li@intel.com
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190418100634.984-1-tvrtko.ursulin@linux.intel.com
Fixes:
|
||
|---|---|---|
| .. | ||
| intel_breadcrumbs.c | ||
| intel_context_types.h | ||
| intel_context.c | ||
| intel_context.h | ||
| intel_engine_cs.c | ||
| intel_engine_pm.c | ||
| intel_engine_pm.h | ||
| intel_engine_types.h | ||
| intel_engine.h | ||
| intel_gpu_commands.h | ||
| intel_gt_pm.c | ||
| intel_gt_pm.h | ||
| intel_hangcheck.c | ||
| intel_lrc_reg.h | ||
| intel_lrc.c | ||
| intel_lrc.h | ||
| intel_mocs.c | ||
| intel_mocs.h | ||
| intel_reset.c | ||
| intel_reset.h | ||
| intel_ringbuffer.c | ||
| intel_sseu.c | ||
| intel_sseu.h | ||
| intel_workarounds_types.h | ||
| intel_workarounds.c | ||
| intel_workarounds.h | ||
| Makefile | ||
| Makefile.header-test | ||
| mock_engine.c | ||
| mock_engine.h | ||
| selftest_engine_cs.c | ||
| selftest_hangcheck.c | ||
| selftest_lrc.c | ||
| selftest_workarounds.c | ||