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07590ff039
Extentions to RapidIO switch support: 1. modify switch route operation declarations to allow using single switch-specific file for family of switches that share the same route table operations. 2. add standard route table operations for switches that that support route table manipulation registers as defined in the Rev.1.3 of RapidIO specification. 3. add clear-route-table operation for switches 4. add CPSxx and TSIxxx families of RapidIO switches Signed-off-by: Alexandre Bounine <alexandre.bounine@idt.com> Tested-by: Thomas Moll <thomas.moll@sysgo.com> Cc: Matt Porter <mporter@kernel.crashing.org> Cc: Li Yang <leoli@freescale.com> Cc: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
226 lines
11 KiB
C
226 lines
11 KiB
C
/*
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* RapidIO register definitions
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*
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* Copyright 2005 MontaVista Software, Inc.
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* Matt Porter <mporter@kernel.crashing.org>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#ifndef LINUX_RIO_REGS_H
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#define LINUX_RIO_REGS_H
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/*
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* In RapidIO, each device has a 2MB configuration space that is
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* accessed via maintenance transactions. Portions of configuration
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* space are standardized and/or reserved.
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*/
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#define RIO_DEV_ID_CAR 0x00 /* [I] Device Identity CAR */
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#define RIO_DEV_INFO_CAR 0x04 /* [I] Device Information CAR */
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#define RIO_ASM_ID_CAR 0x08 /* [I] Assembly Identity CAR */
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#define RIO_ASM_ID_MASK 0xffff0000 /* [I] Asm ID Mask */
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#define RIO_ASM_VEN_ID_MASK 0x0000ffff /* [I] Asm Vend Mask */
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#define RIO_ASM_INFO_CAR 0x0c /* [I] Assembly Information CAR */
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#define RIO_ASM_REV_MASK 0xffff0000 /* [I] Asm Rev Mask */
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#define RIO_EXT_FTR_PTR_MASK 0x0000ffff /* [I] EF_PTR Mask */
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#define RIO_PEF_CAR 0x10 /* [I] Processing Element Features CAR */
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#define RIO_PEF_BRIDGE 0x80000000 /* [I] Bridge */
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#define RIO_PEF_MEMORY 0x40000000 /* [I] MMIO */
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#define RIO_PEF_PROCESSOR 0x20000000 /* [I] Processor */
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#define RIO_PEF_SWITCH 0x10000000 /* [I] Switch */
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#define RIO_PEF_INB_MBOX 0x00f00000 /* [II] Mailboxes */
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#define RIO_PEF_INB_MBOX0 0x00800000 /* [II] Mailbox 0 */
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#define RIO_PEF_INB_MBOX1 0x00400000 /* [II] Mailbox 1 */
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#define RIO_PEF_INB_MBOX2 0x00200000 /* [II] Mailbox 2 */
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#define RIO_PEF_INB_MBOX3 0x00100000 /* [II] Mailbox 3 */
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#define RIO_PEF_INB_DOORBELL 0x00080000 /* [II] Doorbells */
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#define RIO_PEF_EXT_RT 0x00000200 /* [III, 1.3] Extended route table support */
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#define RIO_PEF_STD_RT 0x00000100 /* [III, 1.3] Standard route table support */
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#define RIO_PEF_CTLS 0x00000010 /* [III] CTLS */
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#define RIO_PEF_EXT_FEATURES 0x00000008 /* [I] EFT_PTR valid */
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#define RIO_PEF_ADDR_66 0x00000004 /* [I] 66 bits */
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#define RIO_PEF_ADDR_50 0x00000002 /* [I] 50 bits */
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#define RIO_PEF_ADDR_34 0x00000001 /* [I] 34 bits */
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#define RIO_SWP_INFO_CAR 0x14 /* [I] Switch Port Information CAR */
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#define RIO_SWP_INFO_PORT_TOTAL_MASK 0x0000ff00 /* [I] Total number of ports */
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#define RIO_SWP_INFO_PORT_NUM_MASK 0x000000ff /* [I] Maintenance transaction port number */
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#define RIO_GET_TOTAL_PORTS(x) ((x & RIO_SWP_INFO_PORT_TOTAL_MASK) >> 8)
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#define RIO_SRC_OPS_CAR 0x18 /* [I] Source Operations CAR */
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#define RIO_SRC_OPS_READ 0x00008000 /* [I] Read op */
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#define RIO_SRC_OPS_WRITE 0x00004000 /* [I] Write op */
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#define RIO_SRC_OPS_STREAM_WRITE 0x00002000 /* [I] Str-write op */
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#define RIO_SRC_OPS_WRITE_RESPONSE 0x00001000 /* [I] Write/resp op */
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#define RIO_SRC_OPS_DATA_MSG 0x00000800 /* [II] Data msg op */
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#define RIO_SRC_OPS_DOORBELL 0x00000400 /* [II] Doorbell op */
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#define RIO_SRC_OPS_ATOMIC_TST_SWP 0x00000100 /* [I] Atomic TAS op */
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#define RIO_SRC_OPS_ATOMIC_INC 0x00000080 /* [I] Atomic inc op */
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#define RIO_SRC_OPS_ATOMIC_DEC 0x00000040 /* [I] Atomic dec op */
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#define RIO_SRC_OPS_ATOMIC_SET 0x00000020 /* [I] Atomic set op */
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#define RIO_SRC_OPS_ATOMIC_CLR 0x00000010 /* [I] Atomic clr op */
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#define RIO_SRC_OPS_PORT_WRITE 0x00000004 /* [I] Port-write op */
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#define RIO_DST_OPS_CAR 0x1c /* Destination Operations CAR */
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#define RIO_DST_OPS_READ 0x00008000 /* [I] Read op */
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#define RIO_DST_OPS_WRITE 0x00004000 /* [I] Write op */
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#define RIO_DST_OPS_STREAM_WRITE 0x00002000 /* [I] Str-write op */
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#define RIO_DST_OPS_WRITE_RESPONSE 0x00001000 /* [I] Write/resp op */
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#define RIO_DST_OPS_DATA_MSG 0x00000800 /* [II] Data msg op */
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#define RIO_DST_OPS_DOORBELL 0x00000400 /* [II] Doorbell op */
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#define RIO_DST_OPS_ATOMIC_TST_SWP 0x00000100 /* [I] Atomic TAS op */
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#define RIO_DST_OPS_ATOMIC_INC 0x00000080 /* [I] Atomic inc op */
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#define RIO_DST_OPS_ATOMIC_DEC 0x00000040 /* [I] Atomic dec op */
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#define RIO_DST_OPS_ATOMIC_SET 0x00000020 /* [I] Atomic set op */
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#define RIO_DST_OPS_ATOMIC_CLR 0x00000010 /* [I] Atomic clr op */
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#define RIO_DST_OPS_PORT_WRITE 0x00000004 /* [I] Port-write op */
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#define RIO_OPS_READ 0x00008000 /* [I] Read op */
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#define RIO_OPS_WRITE 0x00004000 /* [I] Write op */
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#define RIO_OPS_STREAM_WRITE 0x00002000 /* [I] Str-write op */
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#define RIO_OPS_WRITE_RESPONSE 0x00001000 /* [I] Write/resp op */
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#define RIO_OPS_DATA_MSG 0x00000800 /* [II] Data msg op */
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#define RIO_OPS_DOORBELL 0x00000400 /* [II] Doorbell op */
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#define RIO_OPS_ATOMIC_TST_SWP 0x00000100 /* [I] Atomic TAS op */
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#define RIO_OPS_ATOMIC_INC 0x00000080 /* [I] Atomic inc op */
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#define RIO_OPS_ATOMIC_DEC 0x00000040 /* [I] Atomic dec op */
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#define RIO_OPS_ATOMIC_SET 0x00000020 /* [I] Atomic set op */
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#define RIO_OPS_ATOMIC_CLR 0x00000010 /* [I] Atomic clr op */
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#define RIO_OPS_PORT_WRITE 0x00000004 /* [I] Port-write op */
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/* 0x20-0x30 *//* Reserved */
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#define RIO_SWITCH_RT_LIMIT 0x34 /* [III, 1.3] Switch Route Table Destination ID Limit CAR */
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#define RIO_RT_MAX_DESTID 0x0000ffff
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#define RIO_MBOX_CSR 0x40 /* [II] Mailbox CSR */
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#define RIO_MBOX0_AVAIL 0x80000000 /* [II] Mbox 0 avail */
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#define RIO_MBOX0_FULL 0x40000000 /* [II] Mbox 0 full */
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#define RIO_MBOX0_EMPTY 0x20000000 /* [II] Mbox 0 empty */
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#define RIO_MBOX0_BUSY 0x10000000 /* [II] Mbox 0 busy */
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#define RIO_MBOX0_FAIL 0x08000000 /* [II] Mbox 0 fail */
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#define RIO_MBOX0_ERROR 0x04000000 /* [II] Mbox 0 error */
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#define RIO_MBOX1_AVAIL 0x00800000 /* [II] Mbox 1 avail */
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#define RIO_MBOX1_FULL 0x00200000 /* [II] Mbox 1 full */
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#define RIO_MBOX1_EMPTY 0x00200000 /* [II] Mbox 1 empty */
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#define RIO_MBOX1_BUSY 0x00100000 /* [II] Mbox 1 busy */
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#define RIO_MBOX1_FAIL 0x00080000 /* [II] Mbox 1 fail */
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#define RIO_MBOX1_ERROR 0x00040000 /* [II] Mbox 1 error */
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#define RIO_MBOX2_AVAIL 0x00008000 /* [II] Mbox 2 avail */
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#define RIO_MBOX2_FULL 0x00004000 /* [II] Mbox 2 full */
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#define RIO_MBOX2_EMPTY 0x00002000 /* [II] Mbox 2 empty */
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#define RIO_MBOX2_BUSY 0x00001000 /* [II] Mbox 2 busy */
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#define RIO_MBOX2_FAIL 0x00000800 /* [II] Mbox 2 fail */
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#define RIO_MBOX2_ERROR 0x00000400 /* [II] Mbox 2 error */
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#define RIO_MBOX3_AVAIL 0x00000080 /* [II] Mbox 3 avail */
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#define RIO_MBOX3_FULL 0x00000040 /* [II] Mbox 3 full */
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#define RIO_MBOX3_EMPTY 0x00000020 /* [II] Mbox 3 empty */
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#define RIO_MBOX3_BUSY 0x00000010 /* [II] Mbox 3 busy */
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#define RIO_MBOX3_FAIL 0x00000008 /* [II] Mbox 3 fail */
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#define RIO_MBOX3_ERROR 0x00000004 /* [II] Mbox 3 error */
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#define RIO_WRITE_PORT_CSR 0x44 /* [I] Write Port CSR */
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#define RIO_DOORBELL_CSR 0x44 /* [II] Doorbell CSR */
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#define RIO_DOORBELL_AVAIL 0x80000000 /* [II] Doorbell avail */
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#define RIO_DOORBELL_FULL 0x40000000 /* [II] Doorbell full */
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#define RIO_DOORBELL_EMPTY 0x20000000 /* [II] Doorbell empty */
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#define RIO_DOORBELL_BUSY 0x10000000 /* [II] Doorbell busy */
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#define RIO_DOORBELL_FAILED 0x08000000 /* [II] Doorbell failed */
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#define RIO_DOORBELL_ERROR 0x04000000 /* [II] Doorbell error */
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#define RIO_WRITE_PORT_AVAILABLE 0x00000080 /* [I] Write Port Available */
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#define RIO_WRITE_PORT_FULL 0x00000040 /* [I] Write Port Full */
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#define RIO_WRITE_PORT_EMPTY 0x00000020 /* [I] Write Port Empty */
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#define RIO_WRITE_PORT_BUSY 0x00000010 /* [I] Write Port Busy */
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#define RIO_WRITE_PORT_FAILED 0x00000008 /* [I] Write Port Failed */
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#define RIO_WRITE_PORT_ERROR 0x00000004 /* [I] Write Port Error */
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/* 0x48 *//* Reserved */
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#define RIO_PELL_CTRL_CSR 0x4c /* [I] PE Logical Layer Control CSR */
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#define RIO_PELL_ADDR_66 0x00000004 /* [I] 66-bit addr */
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#define RIO_PELL_ADDR_50 0x00000002 /* [I] 50-bit addr */
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#define RIO_PELL_ADDR_34 0x00000001 /* [I] 34-bit addr */
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/* 0x50-0x54 *//* Reserved */
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#define RIO_LCSH_BA 0x58 /* [I] LCS High Base Address */
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#define RIO_LCSL_BA 0x5c /* [I] LCS Base Address */
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#define RIO_DID_CSR 0x60 /* [III] Base Device ID CSR */
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/* 0x64 *//* Reserved */
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#define RIO_HOST_DID_LOCK_CSR 0x68 /* [III] Host Base Device ID Lock CSR */
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#define RIO_COMPONENT_TAG_CSR 0x6c /* [III] Component Tag CSR */
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#define RIO_STD_RTE_CONF_DESTID_SEL_CSR 0x70
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#define RIO_STD_RTE_CONF_PORT_SEL_CSR 0x74
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#define RIO_STD_RTE_DEFAULT_PORT 0x78
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/* 0x7c-0xf8 *//* Reserved */
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/* 0x100-0xfff8 *//* [I] Extended Features Space */
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/* 0x10000-0xfffff8 *//* [I] Implementation-defined Space */
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/*
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* Extended Features Space is a configuration space area where
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* functionality is mapped into extended feature blocks via a
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* singly linked list of extended feature pointers (EFT_PTR).
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*
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* Each extended feature block can be identified/located in
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* Extended Features Space by walking the extended feature
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* list starting with the Extended Feature Pointer located
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* in the Assembly Information CAR.
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*
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* Extended Feature Blocks (EFBs) are identified with an assigned
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* EFB ID. Extended feature block offsets in the definitions are
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* relative to the offset of the EFB within the Extended Features
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* Space.
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*/
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/* Helper macros to parse the Extended Feature Block header */
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#define RIO_EFB_PTR_MASK 0xffff0000
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#define RIO_EFB_ID_MASK 0x0000ffff
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#define RIO_GET_BLOCK_PTR(x) ((x & RIO_EFB_PTR_MASK) >> 16)
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#define RIO_GET_BLOCK_ID(x) (x & RIO_EFB_ID_MASK)
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/* Extended Feature Block IDs */
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#define RIO_EFB_PAR_EP_ID 0x0001 /* [IV] LP/LVDS EP Devices */
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#define RIO_EFB_PAR_EP_REC_ID 0x0002 /* [IV] LP/LVDS EP Recovery Devices */
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#define RIO_EFB_PAR_EP_FREE_ID 0x0003 /* [IV] LP/LVDS EP Free Devices */
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#define RIO_EFB_SER_EP_ID 0x0004 /* [VI] LP/Serial EP Devices */
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#define RIO_EFB_SER_EP_REC_ID 0x0005 /* [VI] LP/Serial EP Recovery Devices */
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#define RIO_EFB_SER_EP_FREE_ID 0x0006 /* [VI] LP/Serial EP Free Devices */
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#define RIO_EFB_SER_EP_FREC_ID 0x0009 /* [VI] LP/Serial EP Free Recovery Devices */
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/*
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* Physical 8/16 LP-LVDS
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* ID=0x0001, Generic End Point Devices
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* ID=0x0002, Generic End Point Devices, software assisted recovery option
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* ID=0x0003, Generic End Point Free Devices
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*
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* Physical LP-Serial
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* ID=0x0004, Generic End Point Devices
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* ID=0x0005, Generic End Point Devices, software assisted recovery option
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* ID=0x0006, Generic End Point Free Devices
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*/
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#define RIO_PORT_MNT_HEADER 0x0000
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#define RIO_PORT_REQ_CTL_CSR 0x0020
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#define RIO_PORT_RSP_CTL_CSR 0x0024 /* 0x0001/0x0002 */
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#define RIO_PORT_GEN_CTL_CSR 0x003c
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#define RIO_PORT_GEN_HOST 0x80000000
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#define RIO_PORT_GEN_MASTER 0x40000000
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#define RIO_PORT_GEN_DISCOVERED 0x20000000
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#define RIO_PORT_N_MNT_REQ_CSR(x) (0x0040 + x*0x20) /* 0x0002 */
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#define RIO_PORT_N_MNT_RSP_CSR(x) (0x0044 + x*0x20) /* 0x0002 */
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#define RIO_PORT_N_ACK_STS_CSR(x) (0x0048 + x*0x20) /* 0x0002 */
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#define RIO_PORT_N_ERR_STS_CSR(x) (0x58 + x*0x20)
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#define PORT_N_ERR_STS_PORT_OK 0x00000002
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#define RIO_PORT_N_CTL_CSR(x) (0x5c + x*0x20)
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#endif /* LINUX_RIO_REGS_H */
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