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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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3e98d829ad
include ttm_bo_move_memcpy and ttm_bo_move_ttm Signed-off-by: Roger He <Hongbo.He@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
1934 lines
49 KiB
C
1934 lines
49 KiB
C
/*
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* Copyright 2009 Jerome Glisse.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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*/
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/*
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* Authors:
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* Jerome Glisse <glisse@freedesktop.org>
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* Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
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* Dave Airlie
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*/
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#include <drm/ttm/ttm_bo_api.h>
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#include <drm/ttm/ttm_bo_driver.h>
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#include <drm/ttm/ttm_placement.h>
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#include <drm/ttm/ttm_module.h>
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#include <drm/ttm/ttm_page_alloc.h>
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#include <drm/drmP.h>
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#include <drm/amdgpu_drm.h>
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#include <linux/seq_file.h>
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#include <linux/slab.h>
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#include <linux/swiotlb.h>
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#include <linux/swap.h>
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#include <linux/pagemap.h>
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#include <linux/debugfs.h>
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#include <linux/iommu.h>
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#include "amdgpu.h"
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#include "amdgpu_object.h"
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#include "amdgpu_trace.h"
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#include "bif/bif_4_1_d.h"
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#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
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static int amdgpu_map_buffer(struct ttm_buffer_object *bo,
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struct ttm_mem_reg *mem, unsigned num_pages,
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uint64_t offset, unsigned window,
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struct amdgpu_ring *ring,
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uint64_t *addr);
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static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev);
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static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev);
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/*
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* Global memory.
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*/
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static int amdgpu_ttm_mem_global_init(struct drm_global_reference *ref)
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{
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return ttm_mem_global_init(ref->object);
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}
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static void amdgpu_ttm_mem_global_release(struct drm_global_reference *ref)
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{
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ttm_mem_global_release(ref->object);
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}
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static int amdgpu_ttm_global_init(struct amdgpu_device *adev)
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{
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struct drm_global_reference *global_ref;
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struct amdgpu_ring *ring;
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struct drm_sched_rq *rq;
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int r;
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adev->mman.mem_global_referenced = false;
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global_ref = &adev->mman.mem_global_ref;
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global_ref->global_type = DRM_GLOBAL_TTM_MEM;
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global_ref->size = sizeof(struct ttm_mem_global);
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global_ref->init = &amdgpu_ttm_mem_global_init;
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global_ref->release = &amdgpu_ttm_mem_global_release;
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r = drm_global_item_ref(global_ref);
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if (r) {
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DRM_ERROR("Failed setting up TTM memory accounting "
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"subsystem.\n");
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goto error_mem;
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}
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adev->mman.bo_global_ref.mem_glob =
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adev->mman.mem_global_ref.object;
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global_ref = &adev->mman.bo_global_ref.ref;
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global_ref->global_type = DRM_GLOBAL_TTM_BO;
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global_ref->size = sizeof(struct ttm_bo_global);
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global_ref->init = &ttm_bo_global_init;
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global_ref->release = &ttm_bo_global_release;
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r = drm_global_item_ref(global_ref);
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if (r) {
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DRM_ERROR("Failed setting up TTM BO subsystem.\n");
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goto error_bo;
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}
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mutex_init(&adev->mman.gtt_window_lock);
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ring = adev->mman.buffer_funcs_ring;
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rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_KERNEL];
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r = drm_sched_entity_init(&ring->sched, &adev->mman.entity,
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rq, amdgpu_sched_jobs, NULL);
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if (r) {
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DRM_ERROR("Failed setting up TTM BO move run queue.\n");
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goto error_entity;
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}
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adev->mman.mem_global_referenced = true;
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return 0;
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error_entity:
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drm_global_item_unref(&adev->mman.bo_global_ref.ref);
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error_bo:
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drm_global_item_unref(&adev->mman.mem_global_ref);
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error_mem:
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return r;
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}
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static void amdgpu_ttm_global_fini(struct amdgpu_device *adev)
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{
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if (adev->mman.mem_global_referenced) {
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drm_sched_entity_fini(adev->mman.entity.sched,
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&adev->mman.entity);
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mutex_destroy(&adev->mman.gtt_window_lock);
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drm_global_item_unref(&adev->mman.bo_global_ref.ref);
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drm_global_item_unref(&adev->mman.mem_global_ref);
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adev->mman.mem_global_referenced = false;
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}
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}
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static int amdgpu_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
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{
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return 0;
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}
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static int amdgpu_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
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struct ttm_mem_type_manager *man)
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{
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struct amdgpu_device *adev;
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adev = amdgpu_ttm_adev(bdev);
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switch (type) {
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case TTM_PL_SYSTEM:
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/* System memory */
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man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
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man->available_caching = TTM_PL_MASK_CACHING;
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man->default_caching = TTM_PL_FLAG_CACHED;
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break;
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case TTM_PL_TT:
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man->func = &amdgpu_gtt_mgr_func;
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man->gpu_offset = adev->mc.gart_start;
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man->available_caching = TTM_PL_MASK_CACHING;
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man->default_caching = TTM_PL_FLAG_CACHED;
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man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
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break;
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case TTM_PL_VRAM:
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/* "On-card" video ram */
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man->func = &amdgpu_vram_mgr_func;
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man->gpu_offset = adev->mc.vram_start;
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man->flags = TTM_MEMTYPE_FLAG_FIXED |
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TTM_MEMTYPE_FLAG_MAPPABLE;
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man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
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man->default_caching = TTM_PL_FLAG_WC;
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break;
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case AMDGPU_PL_GDS:
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case AMDGPU_PL_GWS:
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case AMDGPU_PL_OA:
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/* On-chip GDS memory*/
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man->func = &ttm_bo_manager_func;
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man->gpu_offset = 0;
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man->flags = TTM_MEMTYPE_FLAG_FIXED | TTM_MEMTYPE_FLAG_CMA;
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man->available_caching = TTM_PL_FLAG_UNCACHED;
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man->default_caching = TTM_PL_FLAG_UNCACHED;
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break;
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default:
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DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
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return -EINVAL;
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}
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return 0;
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}
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static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
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struct ttm_placement *placement)
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{
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struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
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struct amdgpu_bo *abo;
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static const struct ttm_place placements = {
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.fpfn = 0,
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.lpfn = 0,
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.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM
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};
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if (!amdgpu_ttm_bo_is_amdgpu_bo(bo)) {
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placement->placement = &placements;
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placement->busy_placement = &placements;
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placement->num_placement = 1;
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placement->num_busy_placement = 1;
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return;
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}
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abo = ttm_to_amdgpu_bo(bo);
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switch (bo->mem.mem_type) {
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case TTM_PL_VRAM:
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if (adev->mman.buffer_funcs &&
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adev->mman.buffer_funcs_ring &&
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adev->mman.buffer_funcs_ring->ready == false) {
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amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
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} else if (adev->mc.visible_vram_size < adev->mc.real_vram_size &&
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!(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)) {
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unsigned fpfn = adev->mc.visible_vram_size >> PAGE_SHIFT;
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struct drm_mm_node *node = bo->mem.mm_node;
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unsigned long pages_left;
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for (pages_left = bo->mem.num_pages;
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pages_left;
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pages_left -= node->size, node++) {
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if (node->start < fpfn)
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break;
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}
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if (!pages_left)
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goto gtt;
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/* Try evicting to the CPU inaccessible part of VRAM
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* first, but only set GTT as busy placement, so this
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* BO will be evicted to GTT rather than causing other
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* BOs to be evicted from VRAM
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*/
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amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
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AMDGPU_GEM_DOMAIN_GTT);
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abo->placements[0].fpfn = fpfn;
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abo->placements[0].lpfn = 0;
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abo->placement.busy_placement = &abo->placements[1];
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abo->placement.num_busy_placement = 1;
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} else {
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gtt:
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amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT);
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}
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break;
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case TTM_PL_TT:
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default:
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amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
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}
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*placement = abo->placement;
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}
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static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp)
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{
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struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
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if (amdgpu_ttm_tt_get_usermm(bo->ttm))
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return -EPERM;
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return drm_vma_node_verify_access(&abo->gem_base.vma_node,
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filp->private_data);
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}
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static void amdgpu_move_null(struct ttm_buffer_object *bo,
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struct ttm_mem_reg *new_mem)
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{
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struct ttm_mem_reg *old_mem = &bo->mem;
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BUG_ON(old_mem->mm_node != NULL);
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*old_mem = *new_mem;
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new_mem->mm_node = NULL;
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}
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static uint64_t amdgpu_mm_node_addr(struct ttm_buffer_object *bo,
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struct drm_mm_node *mm_node,
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struct ttm_mem_reg *mem)
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{
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uint64_t addr = 0;
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if (mem->mem_type != TTM_PL_TT || amdgpu_gtt_mgr_has_gart_addr(mem)) {
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addr = mm_node->start << PAGE_SHIFT;
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addr += bo->bdev->man[mem->mem_type].gpu_offset;
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}
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return addr;
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}
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/**
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* amdgpu_find_mm_node - Helper function finds the drm_mm_node
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* corresponding to @offset. It also modifies the offset to be
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* within the drm_mm_node returned
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*/
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static struct drm_mm_node *amdgpu_find_mm_node(struct ttm_mem_reg *mem,
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unsigned long *offset)
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{
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struct drm_mm_node *mm_node = mem->mm_node;
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while (*offset >= (mm_node->size << PAGE_SHIFT)) {
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*offset -= (mm_node->size << PAGE_SHIFT);
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++mm_node;
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}
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return mm_node;
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}
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/**
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* amdgpu_copy_ttm_mem_to_mem - Helper function for copy
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*
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* The function copies @size bytes from {src->mem + src->offset} to
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* {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a
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* move and different for a BO to BO copy.
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*
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* @f: Returns the last fence if multiple jobs are submitted.
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*/
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int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
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struct amdgpu_copy_mem *src,
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struct amdgpu_copy_mem *dst,
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uint64_t size,
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struct reservation_object *resv,
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struct dma_fence **f)
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{
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struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
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struct drm_mm_node *src_mm, *dst_mm;
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uint64_t src_node_start, dst_node_start, src_node_size,
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dst_node_size, src_page_offset, dst_page_offset;
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struct dma_fence *fence = NULL;
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int r = 0;
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const uint64_t GTT_MAX_BYTES = (AMDGPU_GTT_MAX_TRANSFER_SIZE *
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AMDGPU_GPU_PAGE_SIZE);
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if (!ring->ready) {
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DRM_ERROR("Trying to move memory with ring turned off.\n");
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return -EINVAL;
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}
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src_mm = amdgpu_find_mm_node(src->mem, &src->offset);
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src_node_start = amdgpu_mm_node_addr(src->bo, src_mm, src->mem) +
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src->offset;
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src_node_size = (src_mm->size << PAGE_SHIFT) - src->offset;
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src_page_offset = src_node_start & (PAGE_SIZE - 1);
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dst_mm = amdgpu_find_mm_node(dst->mem, &dst->offset);
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dst_node_start = amdgpu_mm_node_addr(dst->bo, dst_mm, dst->mem) +
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dst->offset;
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dst_node_size = (dst_mm->size << PAGE_SHIFT) - dst->offset;
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dst_page_offset = dst_node_start & (PAGE_SIZE - 1);
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mutex_lock(&adev->mman.gtt_window_lock);
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while (size) {
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unsigned long cur_size;
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uint64_t from = src_node_start, to = dst_node_start;
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struct dma_fence *next;
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/* Copy size cannot exceed GTT_MAX_BYTES. So if src or dst
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* begins at an offset, then adjust the size accordingly
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*/
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cur_size = min3(min(src_node_size, dst_node_size), size,
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GTT_MAX_BYTES);
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if (cur_size + src_page_offset > GTT_MAX_BYTES ||
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cur_size + dst_page_offset > GTT_MAX_BYTES)
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cur_size -= max(src_page_offset, dst_page_offset);
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/* Map only what needs to be accessed. Map src to window 0 and
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* dst to window 1
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*/
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if (src->mem->mem_type == TTM_PL_TT &&
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!amdgpu_gtt_mgr_has_gart_addr(src->mem)) {
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r = amdgpu_map_buffer(src->bo, src->mem,
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PFN_UP(cur_size + src_page_offset),
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src_node_start, 0, ring,
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&from);
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if (r)
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goto error;
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/* Adjust the offset because amdgpu_map_buffer returns
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* start of mapped page
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*/
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from += src_page_offset;
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}
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if (dst->mem->mem_type == TTM_PL_TT &&
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!amdgpu_gtt_mgr_has_gart_addr(dst->mem)) {
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r = amdgpu_map_buffer(dst->bo, dst->mem,
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PFN_UP(cur_size + dst_page_offset),
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dst_node_start, 1, ring,
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&to);
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if (r)
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goto error;
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to += dst_page_offset;
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}
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r = amdgpu_copy_buffer(ring, from, to, cur_size,
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resv, &next, false, true);
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if (r)
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goto error;
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dma_fence_put(fence);
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fence = next;
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size -= cur_size;
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if (!size)
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break;
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src_node_size -= cur_size;
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if (!src_node_size) {
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src_node_start = amdgpu_mm_node_addr(src->bo, ++src_mm,
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src->mem);
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src_node_size = (src_mm->size << PAGE_SHIFT);
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} else {
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src_node_start += cur_size;
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src_page_offset = src_node_start & (PAGE_SIZE - 1);
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}
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dst_node_size -= cur_size;
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if (!dst_node_size) {
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dst_node_start = amdgpu_mm_node_addr(dst->bo, ++dst_mm,
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dst->mem);
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dst_node_size = (dst_mm->size << PAGE_SHIFT);
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} else {
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dst_node_start += cur_size;
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dst_page_offset = dst_node_start & (PAGE_SIZE - 1);
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}
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}
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error:
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mutex_unlock(&adev->mman.gtt_window_lock);
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if (f)
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*f = dma_fence_get(fence);
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dma_fence_put(fence);
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return r;
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}
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static int amdgpu_move_blit(struct ttm_buffer_object *bo,
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bool evict, bool no_wait_gpu,
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struct ttm_mem_reg *new_mem,
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struct ttm_mem_reg *old_mem)
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{
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struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
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struct amdgpu_copy_mem src, dst;
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struct dma_fence *fence = NULL;
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int r;
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src.bo = bo;
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dst.bo = bo;
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src.mem = old_mem;
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dst.mem = new_mem;
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src.offset = 0;
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dst.offset = 0;
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|
|
r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst,
|
|
new_mem->num_pages << PAGE_SHIFT,
|
|
bo->resv, &fence);
|
|
if (r)
|
|
goto error;
|
|
|
|
r = ttm_bo_pipeline_move(bo, fence, evict, new_mem);
|
|
dma_fence_put(fence);
|
|
return r;
|
|
|
|
error:
|
|
if (fence)
|
|
dma_fence_wait(fence, false);
|
|
dma_fence_put(fence);
|
|
return r;
|
|
}
|
|
|
|
static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo, bool evict,
|
|
struct ttm_operation_ctx *ctx,
|
|
struct ttm_mem_reg *new_mem)
|
|
{
|
|
struct amdgpu_device *adev;
|
|
struct ttm_mem_reg *old_mem = &bo->mem;
|
|
struct ttm_mem_reg tmp_mem;
|
|
struct ttm_place placements;
|
|
struct ttm_placement placement;
|
|
int r;
|
|
|
|
adev = amdgpu_ttm_adev(bo->bdev);
|
|
tmp_mem = *new_mem;
|
|
tmp_mem.mm_node = NULL;
|
|
placement.num_placement = 1;
|
|
placement.placement = &placements;
|
|
placement.num_busy_placement = 1;
|
|
placement.busy_placement = &placements;
|
|
placements.fpfn = 0;
|
|
placements.lpfn = 0;
|
|
placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
|
|
r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);
|
|
if (unlikely(r)) {
|
|
return r;
|
|
}
|
|
|
|
r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
|
|
if (unlikely(r)) {
|
|
goto out_cleanup;
|
|
}
|
|
|
|
r = ttm_tt_bind(bo->ttm, &tmp_mem);
|
|
if (unlikely(r)) {
|
|
goto out_cleanup;
|
|
}
|
|
r = amdgpu_move_blit(bo, true, ctx->no_wait_gpu, &tmp_mem, old_mem);
|
|
if (unlikely(r)) {
|
|
goto out_cleanup;
|
|
}
|
|
r = ttm_bo_move_ttm(bo, ctx, new_mem);
|
|
out_cleanup:
|
|
ttm_bo_mem_put(bo, &tmp_mem);
|
|
return r;
|
|
}
|
|
|
|
static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo, bool evict,
|
|
struct ttm_operation_ctx *ctx,
|
|
struct ttm_mem_reg *new_mem)
|
|
{
|
|
struct amdgpu_device *adev;
|
|
struct ttm_mem_reg *old_mem = &bo->mem;
|
|
struct ttm_mem_reg tmp_mem;
|
|
struct ttm_placement placement;
|
|
struct ttm_place placements;
|
|
int r;
|
|
|
|
adev = amdgpu_ttm_adev(bo->bdev);
|
|
tmp_mem = *new_mem;
|
|
tmp_mem.mm_node = NULL;
|
|
placement.num_placement = 1;
|
|
placement.placement = &placements;
|
|
placement.num_busy_placement = 1;
|
|
placement.busy_placement = &placements;
|
|
placements.fpfn = 0;
|
|
placements.lpfn = 0;
|
|
placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
|
|
r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);
|
|
if (unlikely(r)) {
|
|
return r;
|
|
}
|
|
r = ttm_bo_move_ttm(bo, ctx, &tmp_mem);
|
|
if (unlikely(r)) {
|
|
goto out_cleanup;
|
|
}
|
|
r = amdgpu_move_blit(bo, true, ctx->no_wait_gpu, new_mem, old_mem);
|
|
if (unlikely(r)) {
|
|
goto out_cleanup;
|
|
}
|
|
out_cleanup:
|
|
ttm_bo_mem_put(bo, &tmp_mem);
|
|
return r;
|
|
}
|
|
|
|
static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict,
|
|
struct ttm_operation_ctx *ctx,
|
|
struct ttm_mem_reg *new_mem)
|
|
{
|
|
struct amdgpu_device *adev;
|
|
struct amdgpu_bo *abo;
|
|
struct ttm_mem_reg *old_mem = &bo->mem;
|
|
int r;
|
|
|
|
/* Can't move a pinned BO */
|
|
abo = ttm_to_amdgpu_bo(bo);
|
|
if (WARN_ON_ONCE(abo->pin_count > 0))
|
|
return -EINVAL;
|
|
|
|
adev = amdgpu_ttm_adev(bo->bdev);
|
|
|
|
if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
|
|
amdgpu_move_null(bo, new_mem);
|
|
return 0;
|
|
}
|
|
if ((old_mem->mem_type == TTM_PL_TT &&
|
|
new_mem->mem_type == TTM_PL_SYSTEM) ||
|
|
(old_mem->mem_type == TTM_PL_SYSTEM &&
|
|
new_mem->mem_type == TTM_PL_TT)) {
|
|
/* bind is enough */
|
|
amdgpu_move_null(bo, new_mem);
|
|
return 0;
|
|
}
|
|
if (adev->mman.buffer_funcs == NULL ||
|
|
adev->mman.buffer_funcs_ring == NULL ||
|
|
!adev->mman.buffer_funcs_ring->ready) {
|
|
/* use memcpy */
|
|
goto memcpy;
|
|
}
|
|
|
|
if (old_mem->mem_type == TTM_PL_VRAM &&
|
|
new_mem->mem_type == TTM_PL_SYSTEM) {
|
|
r = amdgpu_move_vram_ram(bo, evict, ctx, new_mem);
|
|
} else if (old_mem->mem_type == TTM_PL_SYSTEM &&
|
|
new_mem->mem_type == TTM_PL_VRAM) {
|
|
r = amdgpu_move_ram_vram(bo, evict, ctx, new_mem);
|
|
} else {
|
|
r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu,
|
|
new_mem, old_mem);
|
|
}
|
|
|
|
if (r) {
|
|
memcpy:
|
|
r = ttm_bo_move_memcpy(bo, ctx, new_mem);
|
|
if (r) {
|
|
return r;
|
|
}
|
|
}
|
|
|
|
if (bo->type == ttm_bo_type_device &&
|
|
new_mem->mem_type == TTM_PL_VRAM &&
|
|
old_mem->mem_type != TTM_PL_VRAM) {
|
|
/* amdgpu_bo_fault_reserve_notify will re-set this if the CPU
|
|
* accesses the BO after it's moved.
|
|
*/
|
|
abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
|
|
}
|
|
|
|
/* update statistics */
|
|
atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &adev->num_bytes_moved);
|
|
return 0;
|
|
}
|
|
|
|
static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
|
|
{
|
|
struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
|
|
struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
|
|
|
|
mem->bus.addr = NULL;
|
|
mem->bus.offset = 0;
|
|
mem->bus.size = mem->num_pages << PAGE_SHIFT;
|
|
mem->bus.base = 0;
|
|
mem->bus.is_iomem = false;
|
|
if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
|
|
return -EINVAL;
|
|
switch (mem->mem_type) {
|
|
case TTM_PL_SYSTEM:
|
|
/* system memory */
|
|
return 0;
|
|
case TTM_PL_TT:
|
|
break;
|
|
case TTM_PL_VRAM:
|
|
mem->bus.offset = mem->start << PAGE_SHIFT;
|
|
/* check if it's visible */
|
|
if ((mem->bus.offset + mem->bus.size) > adev->mc.visible_vram_size)
|
|
return -EINVAL;
|
|
mem->bus.base = adev->mc.aper_base;
|
|
mem->bus.is_iomem = true;
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static void amdgpu_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
|
|
{
|
|
}
|
|
|
|
static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo,
|
|
unsigned long page_offset)
|
|
{
|
|
struct drm_mm_node *mm;
|
|
unsigned long offset = (page_offset << PAGE_SHIFT);
|
|
|
|
mm = amdgpu_find_mm_node(&bo->mem, &offset);
|
|
return (bo->mem.bus.base >> PAGE_SHIFT) + mm->start +
|
|
(offset >> PAGE_SHIFT);
|
|
}
|
|
|
|
/*
|
|
* TTM backend functions.
|
|
*/
|
|
struct amdgpu_ttm_gup_task_list {
|
|
struct list_head list;
|
|
struct task_struct *task;
|
|
};
|
|
|
|
struct amdgpu_ttm_tt {
|
|
struct ttm_dma_tt ttm;
|
|
struct amdgpu_device *adev;
|
|
u64 offset;
|
|
uint64_t userptr;
|
|
struct mm_struct *usermm;
|
|
uint32_t userflags;
|
|
spinlock_t guptasklock;
|
|
struct list_head guptasks;
|
|
atomic_t mmu_invalidations;
|
|
uint32_t last_set_pages;
|
|
};
|
|
|
|
int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages)
|
|
{
|
|
struct amdgpu_ttm_tt *gtt = (void *)ttm;
|
|
unsigned int flags = 0;
|
|
unsigned pinned = 0;
|
|
int r;
|
|
|
|
if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY))
|
|
flags |= FOLL_WRITE;
|
|
|
|
down_read(¤t->mm->mmap_sem);
|
|
|
|
if (gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) {
|
|
/* check that we only use anonymous memory
|
|
to prevent problems with writeback */
|
|
unsigned long end = gtt->userptr + ttm->num_pages * PAGE_SIZE;
|
|
struct vm_area_struct *vma;
|
|
|
|
vma = find_vma(gtt->usermm, gtt->userptr);
|
|
if (!vma || vma->vm_file || vma->vm_end < end) {
|
|
up_read(¤t->mm->mmap_sem);
|
|
return -EPERM;
|
|
}
|
|
}
|
|
|
|
do {
|
|
unsigned num_pages = ttm->num_pages - pinned;
|
|
uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE;
|
|
struct page **p = pages + pinned;
|
|
struct amdgpu_ttm_gup_task_list guptask;
|
|
|
|
guptask.task = current;
|
|
spin_lock(>t->guptasklock);
|
|
list_add(&guptask.list, >t->guptasks);
|
|
spin_unlock(>t->guptasklock);
|
|
|
|
r = get_user_pages(userptr, num_pages, flags, p, NULL);
|
|
|
|
spin_lock(>t->guptasklock);
|
|
list_del(&guptask.list);
|
|
spin_unlock(>t->guptasklock);
|
|
|
|
if (r < 0)
|
|
goto release_pages;
|
|
|
|
pinned += r;
|
|
|
|
} while (pinned < ttm->num_pages);
|
|
|
|
up_read(¤t->mm->mmap_sem);
|
|
return 0;
|
|
|
|
release_pages:
|
|
release_pages(pages, pinned);
|
|
up_read(¤t->mm->mmap_sem);
|
|
return r;
|
|
}
|
|
|
|
void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages)
|
|
{
|
|
struct amdgpu_ttm_tt *gtt = (void *)ttm;
|
|
unsigned i;
|
|
|
|
gtt->last_set_pages = atomic_read(>t->mmu_invalidations);
|
|
for (i = 0; i < ttm->num_pages; ++i) {
|
|
if (ttm->pages[i])
|
|
put_page(ttm->pages[i]);
|
|
|
|
ttm->pages[i] = pages ? pages[i] : NULL;
|
|
}
|
|
}
|
|
|
|
void amdgpu_ttm_tt_mark_user_pages(struct ttm_tt *ttm)
|
|
{
|
|
struct amdgpu_ttm_tt *gtt = (void *)ttm;
|
|
unsigned i;
|
|
|
|
for (i = 0; i < ttm->num_pages; ++i) {
|
|
struct page *page = ttm->pages[i];
|
|
|
|
if (!page)
|
|
continue;
|
|
|
|
if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY))
|
|
set_page_dirty(page);
|
|
|
|
mark_page_accessed(page);
|
|
}
|
|
}
|
|
|
|
/* prepare the sg table with the user pages */
|
|
static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm)
|
|
{
|
|
struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
|
|
struct amdgpu_ttm_tt *gtt = (void *)ttm;
|
|
unsigned nents;
|
|
int r;
|
|
|
|
int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
|
|
enum dma_data_direction direction = write ?
|
|
DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
|
|
|
|
r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
|
|
ttm->num_pages << PAGE_SHIFT,
|
|
GFP_KERNEL);
|
|
if (r)
|
|
goto release_sg;
|
|
|
|
r = -ENOMEM;
|
|
nents = dma_map_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
|
|
if (nents != ttm->sg->nents)
|
|
goto release_sg;
|
|
|
|
drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
|
|
gtt->ttm.dma_address, ttm->num_pages);
|
|
|
|
return 0;
|
|
|
|
release_sg:
|
|
kfree(ttm->sg);
|
|
return r;
|
|
}
|
|
|
|
static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm)
|
|
{
|
|
struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
|
|
struct amdgpu_ttm_tt *gtt = (void *)ttm;
|
|
|
|
int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
|
|
enum dma_data_direction direction = write ?
|
|
DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
|
|
|
|
/* double check that we don't free the table twice */
|
|
if (!ttm->sg->sgl)
|
|
return;
|
|
|
|
/* free the sg table and pages again */
|
|
dma_unmap_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
|
|
|
|
amdgpu_ttm_tt_mark_user_pages(ttm);
|
|
|
|
sg_free_table(ttm->sg);
|
|
}
|
|
|
|
static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm,
|
|
struct ttm_mem_reg *bo_mem)
|
|
{
|
|
struct amdgpu_ttm_tt *gtt = (void*)ttm;
|
|
uint64_t flags;
|
|
int r = 0;
|
|
|
|
if (gtt->userptr) {
|
|
r = amdgpu_ttm_tt_pin_userptr(ttm);
|
|
if (r) {
|
|
DRM_ERROR("failed to pin userptr\n");
|
|
return r;
|
|
}
|
|
}
|
|
if (!ttm->num_pages) {
|
|
WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
|
|
ttm->num_pages, bo_mem, ttm);
|
|
}
|
|
|
|
if (bo_mem->mem_type == AMDGPU_PL_GDS ||
|
|
bo_mem->mem_type == AMDGPU_PL_GWS ||
|
|
bo_mem->mem_type == AMDGPU_PL_OA)
|
|
return -EINVAL;
|
|
|
|
if (!amdgpu_gtt_mgr_has_gart_addr(bo_mem)) {
|
|
gtt->offset = AMDGPU_BO_INVALID_OFFSET;
|
|
return 0;
|
|
}
|
|
|
|
flags = amdgpu_ttm_tt_pte_flags(gtt->adev, ttm, bo_mem);
|
|
gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
|
|
r = amdgpu_gart_bind(gtt->adev, gtt->offset, ttm->num_pages,
|
|
ttm->pages, gtt->ttm.dma_address, flags);
|
|
|
|
if (r)
|
|
DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
|
|
ttm->num_pages, gtt->offset);
|
|
return r;
|
|
}
|
|
|
|
int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
|
|
{
|
|
struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
|
|
struct ttm_operation_ctx ctx = { false, false };
|
|
struct amdgpu_ttm_tt *gtt = (void*)bo->ttm;
|
|
struct ttm_mem_reg tmp;
|
|
struct ttm_placement placement;
|
|
struct ttm_place placements;
|
|
uint64_t flags;
|
|
int r;
|
|
|
|
if (bo->mem.mem_type != TTM_PL_TT ||
|
|
amdgpu_gtt_mgr_has_gart_addr(&bo->mem))
|
|
return 0;
|
|
|
|
tmp = bo->mem;
|
|
tmp.mm_node = NULL;
|
|
placement.num_placement = 1;
|
|
placement.placement = &placements;
|
|
placement.num_busy_placement = 1;
|
|
placement.busy_placement = &placements;
|
|
placements.fpfn = 0;
|
|
placements.lpfn = adev->mc.gart_size >> PAGE_SHIFT;
|
|
placements.flags = (bo->mem.placement & ~TTM_PL_MASK_MEM) |
|
|
TTM_PL_FLAG_TT;
|
|
|
|
r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx);
|
|
if (unlikely(r))
|
|
return r;
|
|
|
|
flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, &tmp);
|
|
gtt->offset = (u64)tmp.start << PAGE_SHIFT;
|
|
r = amdgpu_gart_bind(adev, gtt->offset, bo->ttm->num_pages,
|
|
bo->ttm->pages, gtt->ttm.dma_address, flags);
|
|
if (unlikely(r)) {
|
|
ttm_bo_mem_put(bo, &tmp);
|
|
return r;
|
|
}
|
|
|
|
ttm_bo_mem_put(bo, &bo->mem);
|
|
bo->mem = tmp;
|
|
bo->offset = (bo->mem.start << PAGE_SHIFT) +
|
|
bo->bdev->man[bo->mem.mem_type].gpu_offset;
|
|
|
|
return 0;
|
|
}
|
|
|
|
int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo)
|
|
{
|
|
struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
|
|
struct amdgpu_ttm_tt *gtt = (void *)tbo->ttm;
|
|
uint64_t flags;
|
|
int r;
|
|
|
|
if (!gtt)
|
|
return 0;
|
|
|
|
flags = amdgpu_ttm_tt_pte_flags(adev, >t->ttm.ttm, &tbo->mem);
|
|
r = amdgpu_gart_bind(adev, gtt->offset, gtt->ttm.ttm.num_pages,
|
|
gtt->ttm.ttm.pages, gtt->ttm.dma_address, flags);
|
|
if (r)
|
|
DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
|
|
gtt->ttm.ttm.num_pages, gtt->offset);
|
|
return r;
|
|
}
|
|
|
|
static int amdgpu_ttm_backend_unbind(struct ttm_tt *ttm)
|
|
{
|
|
struct amdgpu_ttm_tt *gtt = (void *)ttm;
|
|
int r;
|
|
|
|
if (gtt->userptr)
|
|
amdgpu_ttm_tt_unpin_userptr(ttm);
|
|
|
|
if (gtt->offset == AMDGPU_BO_INVALID_OFFSET)
|
|
return 0;
|
|
|
|
/* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
|
|
r = amdgpu_gart_unbind(gtt->adev, gtt->offset, ttm->num_pages);
|
|
if (r)
|
|
DRM_ERROR("failed to unbind %lu pages at 0x%08llX\n",
|
|
gtt->ttm.ttm.num_pages, gtt->offset);
|
|
return r;
|
|
}
|
|
|
|
static void amdgpu_ttm_backend_destroy(struct ttm_tt *ttm)
|
|
{
|
|
struct amdgpu_ttm_tt *gtt = (void *)ttm;
|
|
|
|
ttm_dma_tt_fini(>t->ttm);
|
|
kfree(gtt);
|
|
}
|
|
|
|
static struct ttm_backend_func amdgpu_backend_func = {
|
|
.bind = &amdgpu_ttm_backend_bind,
|
|
.unbind = &amdgpu_ttm_backend_unbind,
|
|
.destroy = &amdgpu_ttm_backend_destroy,
|
|
};
|
|
|
|
static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_bo_device *bdev,
|
|
unsigned long size, uint32_t page_flags,
|
|
struct page *dummy_read_page)
|
|
{
|
|
struct amdgpu_device *adev;
|
|
struct amdgpu_ttm_tt *gtt;
|
|
|
|
adev = amdgpu_ttm_adev(bdev);
|
|
|
|
gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
|
|
if (gtt == NULL) {
|
|
return NULL;
|
|
}
|
|
gtt->ttm.ttm.func = &amdgpu_backend_func;
|
|
gtt->adev = adev;
|
|
if (ttm_dma_tt_init(>t->ttm, bdev, size, page_flags, dummy_read_page)) {
|
|
kfree(gtt);
|
|
return NULL;
|
|
}
|
|
return >t->ttm.ttm;
|
|
}
|
|
|
|
static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm)
|
|
{
|
|
struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
|
|
struct amdgpu_ttm_tt *gtt = (void *)ttm;
|
|
bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
|
|
|
|
if (ttm->state != tt_unpopulated)
|
|
return 0;
|
|
|
|
if (gtt && gtt->userptr) {
|
|
ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
|
|
if (!ttm->sg)
|
|
return -ENOMEM;
|
|
|
|
ttm->page_flags |= TTM_PAGE_FLAG_SG;
|
|
ttm->state = tt_unbound;
|
|
return 0;
|
|
}
|
|
|
|
if (slave && ttm->sg) {
|
|
drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
|
|
gtt->ttm.dma_address, ttm->num_pages);
|
|
ttm->state = tt_unbound;
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_SWIOTLB
|
|
if (swiotlb_nr_tbl()) {
|
|
return ttm_dma_populate(>t->ttm, adev->dev);
|
|
}
|
|
#endif
|
|
|
|
return ttm_populate_and_map_pages(adev->dev, >t->ttm);
|
|
}
|
|
|
|
static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm)
|
|
{
|
|
struct amdgpu_device *adev;
|
|
struct amdgpu_ttm_tt *gtt = (void *)ttm;
|
|
bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
|
|
|
|
if (gtt && gtt->userptr) {
|
|
amdgpu_ttm_tt_set_user_pages(ttm, NULL);
|
|
kfree(ttm->sg);
|
|
ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
|
|
return;
|
|
}
|
|
|
|
if (slave)
|
|
return;
|
|
|
|
adev = amdgpu_ttm_adev(ttm->bdev);
|
|
|
|
#ifdef CONFIG_SWIOTLB
|
|
if (swiotlb_nr_tbl()) {
|
|
ttm_dma_unpopulate(>t->ttm, adev->dev);
|
|
return;
|
|
}
|
|
#endif
|
|
|
|
ttm_unmap_and_unpopulate_pages(adev->dev, >t->ttm);
|
|
}
|
|
|
|
int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
|
|
uint32_t flags)
|
|
{
|
|
struct amdgpu_ttm_tt *gtt = (void *)ttm;
|
|
|
|
if (gtt == NULL)
|
|
return -EINVAL;
|
|
|
|
gtt->userptr = addr;
|
|
gtt->usermm = current->mm;
|
|
gtt->userflags = flags;
|
|
spin_lock_init(>t->guptasklock);
|
|
INIT_LIST_HEAD(>t->guptasks);
|
|
atomic_set(>t->mmu_invalidations, 0);
|
|
gtt->last_set_pages = 0;
|
|
|
|
return 0;
|
|
}
|
|
|
|
struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
|
|
{
|
|
struct amdgpu_ttm_tt *gtt = (void *)ttm;
|
|
|
|
if (gtt == NULL)
|
|
return NULL;
|
|
|
|
return gtt->usermm;
|
|
}
|
|
|
|
bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
|
|
unsigned long end)
|
|
{
|
|
struct amdgpu_ttm_tt *gtt = (void *)ttm;
|
|
struct amdgpu_ttm_gup_task_list *entry;
|
|
unsigned long size;
|
|
|
|
if (gtt == NULL || !gtt->userptr)
|
|
return false;
|
|
|
|
size = (unsigned long)gtt->ttm.ttm.num_pages * PAGE_SIZE;
|
|
if (gtt->userptr > end || gtt->userptr + size <= start)
|
|
return false;
|
|
|
|
spin_lock(>t->guptasklock);
|
|
list_for_each_entry(entry, >t->guptasks, list) {
|
|
if (entry->task == current) {
|
|
spin_unlock(>t->guptasklock);
|
|
return false;
|
|
}
|
|
}
|
|
spin_unlock(>t->guptasklock);
|
|
|
|
atomic_inc(>t->mmu_invalidations);
|
|
|
|
return true;
|
|
}
|
|
|
|
bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
|
|
int *last_invalidated)
|
|
{
|
|
struct amdgpu_ttm_tt *gtt = (void *)ttm;
|
|
int prev_invalidated = *last_invalidated;
|
|
|
|
*last_invalidated = atomic_read(>t->mmu_invalidations);
|
|
return prev_invalidated != *last_invalidated;
|
|
}
|
|
|
|
bool amdgpu_ttm_tt_userptr_needs_pages(struct ttm_tt *ttm)
|
|
{
|
|
struct amdgpu_ttm_tt *gtt = (void *)ttm;
|
|
|
|
if (gtt == NULL || !gtt->userptr)
|
|
return false;
|
|
|
|
return atomic_read(>t->mmu_invalidations) != gtt->last_set_pages;
|
|
}
|
|
|
|
bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
|
|
{
|
|
struct amdgpu_ttm_tt *gtt = (void *)ttm;
|
|
|
|
if (gtt == NULL)
|
|
return false;
|
|
|
|
return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
|
|
}
|
|
|
|
uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
|
|
struct ttm_mem_reg *mem)
|
|
{
|
|
uint64_t flags = 0;
|
|
|
|
if (mem && mem->mem_type != TTM_PL_SYSTEM)
|
|
flags |= AMDGPU_PTE_VALID;
|
|
|
|
if (mem && mem->mem_type == TTM_PL_TT) {
|
|
flags |= AMDGPU_PTE_SYSTEM;
|
|
|
|
if (ttm->caching_state == tt_cached)
|
|
flags |= AMDGPU_PTE_SNOOPED;
|
|
}
|
|
|
|
flags |= adev->gart.gart_pte_flags;
|
|
flags |= AMDGPU_PTE_READABLE;
|
|
|
|
if (!amdgpu_ttm_tt_is_readonly(ttm))
|
|
flags |= AMDGPU_PTE_WRITEABLE;
|
|
|
|
return flags;
|
|
}
|
|
|
|
static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
|
|
const struct ttm_place *place)
|
|
{
|
|
unsigned long num_pages = bo->mem.num_pages;
|
|
struct drm_mm_node *node = bo->mem.mm_node;
|
|
|
|
switch (bo->mem.mem_type) {
|
|
case TTM_PL_TT:
|
|
return true;
|
|
|
|
case TTM_PL_VRAM:
|
|
/* Check each drm MM node individually */
|
|
while (num_pages) {
|
|
if (place->fpfn < (node->start + node->size) &&
|
|
!(place->lpfn && place->lpfn <= node->start))
|
|
return true;
|
|
|
|
num_pages -= node->size;
|
|
++node;
|
|
}
|
|
return false;
|
|
|
|
default:
|
|
break;
|
|
}
|
|
|
|
return ttm_bo_eviction_valuable(bo, place);
|
|
}
|
|
|
|
static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo,
|
|
unsigned long offset,
|
|
void *buf, int len, int write)
|
|
{
|
|
struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
|
|
struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
|
|
struct drm_mm_node *nodes;
|
|
uint32_t value = 0;
|
|
int ret = 0;
|
|
uint64_t pos;
|
|
unsigned long flags;
|
|
|
|
if (bo->mem.mem_type != TTM_PL_VRAM)
|
|
return -EIO;
|
|
|
|
nodes = amdgpu_find_mm_node(&abo->tbo.mem, &offset);
|
|
pos = (nodes->start << PAGE_SHIFT) + offset;
|
|
|
|
while (len && pos < adev->mc.mc_vram_size) {
|
|
uint64_t aligned_pos = pos & ~(uint64_t)3;
|
|
uint32_t bytes = 4 - (pos & 3);
|
|
uint32_t shift = (pos & 3) * 8;
|
|
uint32_t mask = 0xffffffff << shift;
|
|
|
|
if (len < bytes) {
|
|
mask &= 0xffffffff >> (bytes - len) * 8;
|
|
bytes = len;
|
|
}
|
|
|
|
spin_lock_irqsave(&adev->mmio_idx_lock, flags);
|
|
WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)aligned_pos) | 0x80000000);
|
|
WREG32_NO_KIQ(mmMM_INDEX_HI, aligned_pos >> 31);
|
|
if (!write || mask != 0xffffffff)
|
|
value = RREG32_NO_KIQ(mmMM_DATA);
|
|
if (write) {
|
|
value &= ~mask;
|
|
value |= (*(uint32_t *)buf << shift) & mask;
|
|
WREG32_NO_KIQ(mmMM_DATA, value);
|
|
}
|
|
spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
|
|
if (!write) {
|
|
value = (value & mask) >> shift;
|
|
memcpy(buf, &value, bytes);
|
|
}
|
|
|
|
ret += bytes;
|
|
buf = (uint8_t *)buf + bytes;
|
|
pos += bytes;
|
|
len -= bytes;
|
|
if (pos >= (nodes->start + nodes->size) << PAGE_SHIFT) {
|
|
++nodes;
|
|
pos = (nodes->start << PAGE_SHIFT);
|
|
}
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static struct ttm_bo_driver amdgpu_bo_driver = {
|
|
.ttm_tt_create = &amdgpu_ttm_tt_create,
|
|
.ttm_tt_populate = &amdgpu_ttm_tt_populate,
|
|
.ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
|
|
.invalidate_caches = &amdgpu_invalidate_caches,
|
|
.init_mem_type = &amdgpu_init_mem_type,
|
|
.eviction_valuable = amdgpu_ttm_bo_eviction_valuable,
|
|
.evict_flags = &amdgpu_evict_flags,
|
|
.move = &amdgpu_bo_move,
|
|
.verify_access = &amdgpu_verify_access,
|
|
.move_notify = &amdgpu_bo_move_notify,
|
|
.fault_reserve_notify = &amdgpu_bo_fault_reserve_notify,
|
|
.io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
|
|
.io_mem_free = &amdgpu_ttm_io_mem_free,
|
|
.io_mem_pfn = amdgpu_ttm_io_mem_pfn,
|
|
.access_memory = &amdgpu_ttm_access_memory
|
|
};
|
|
|
|
int amdgpu_ttm_init(struct amdgpu_device *adev)
|
|
{
|
|
uint64_t gtt_size;
|
|
int r;
|
|
u64 vis_vram_limit;
|
|
|
|
r = amdgpu_ttm_global_init(adev);
|
|
if (r) {
|
|
return r;
|
|
}
|
|
/* No others user of address space so set it to 0 */
|
|
r = ttm_bo_device_init(&adev->mman.bdev,
|
|
adev->mman.bo_global_ref.ref.object,
|
|
&amdgpu_bo_driver,
|
|
adev->ddev->anon_inode->i_mapping,
|
|
DRM_FILE_PAGE_OFFSET,
|
|
adev->need_dma32);
|
|
if (r) {
|
|
DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
|
|
return r;
|
|
}
|
|
adev->mman.initialized = true;
|
|
r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_VRAM,
|
|
adev->mc.real_vram_size >> PAGE_SHIFT);
|
|
if (r) {
|
|
DRM_ERROR("Failed initializing VRAM heap.\n");
|
|
return r;
|
|
}
|
|
|
|
/* Reduce size of CPU-visible VRAM if requested */
|
|
vis_vram_limit = (u64)amdgpu_vis_vram_limit * 1024 * 1024;
|
|
if (amdgpu_vis_vram_limit > 0 &&
|
|
vis_vram_limit <= adev->mc.visible_vram_size)
|
|
adev->mc.visible_vram_size = vis_vram_limit;
|
|
|
|
/* Change the size here instead of the init above so only lpfn is affected */
|
|
amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
|
|
|
|
/*
|
|
*The reserved vram for firmware must be pinned to the specified
|
|
*place on the VRAM, so reserve it early.
|
|
*/
|
|
r = amdgpu_fw_reserve_vram_init(adev);
|
|
if (r) {
|
|
return r;
|
|
}
|
|
|
|
r = amdgpu_bo_create_kernel(adev, adev->mc.stolen_size, PAGE_SIZE,
|
|
AMDGPU_GEM_DOMAIN_VRAM,
|
|
&adev->stolen_vga_memory,
|
|
NULL, NULL);
|
|
if (r)
|
|
return r;
|
|
DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
|
|
(unsigned) (adev->mc.real_vram_size / (1024 * 1024)));
|
|
|
|
if (amdgpu_gtt_size == -1) {
|
|
struct sysinfo si;
|
|
|
|
si_meminfo(&si);
|
|
gtt_size = max(AMDGPU_DEFAULT_GTT_SIZE_MB << 20,
|
|
(uint64_t)si.totalram * si.mem_unit * 3/4);
|
|
} else
|
|
gtt_size = (uint64_t)amdgpu_gtt_size << 20;
|
|
r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_TT, gtt_size >> PAGE_SHIFT);
|
|
if (r) {
|
|
DRM_ERROR("Failed initializing GTT heap.\n");
|
|
return r;
|
|
}
|
|
DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
|
|
(unsigned)(gtt_size / (1024 * 1024)));
|
|
|
|
adev->gds.mem.total_size = adev->gds.mem.total_size << AMDGPU_GDS_SHIFT;
|
|
adev->gds.mem.gfx_partition_size = adev->gds.mem.gfx_partition_size << AMDGPU_GDS_SHIFT;
|
|
adev->gds.mem.cs_partition_size = adev->gds.mem.cs_partition_size << AMDGPU_GDS_SHIFT;
|
|
adev->gds.gws.total_size = adev->gds.gws.total_size << AMDGPU_GWS_SHIFT;
|
|
adev->gds.gws.gfx_partition_size = adev->gds.gws.gfx_partition_size << AMDGPU_GWS_SHIFT;
|
|
adev->gds.gws.cs_partition_size = adev->gds.gws.cs_partition_size << AMDGPU_GWS_SHIFT;
|
|
adev->gds.oa.total_size = adev->gds.oa.total_size << AMDGPU_OA_SHIFT;
|
|
adev->gds.oa.gfx_partition_size = adev->gds.oa.gfx_partition_size << AMDGPU_OA_SHIFT;
|
|
adev->gds.oa.cs_partition_size = adev->gds.oa.cs_partition_size << AMDGPU_OA_SHIFT;
|
|
/* GDS Memory */
|
|
if (adev->gds.mem.total_size) {
|
|
r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GDS,
|
|
adev->gds.mem.total_size >> PAGE_SHIFT);
|
|
if (r) {
|
|
DRM_ERROR("Failed initializing GDS heap.\n");
|
|
return r;
|
|
}
|
|
}
|
|
|
|
/* GWS */
|
|
if (adev->gds.gws.total_size) {
|
|
r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GWS,
|
|
adev->gds.gws.total_size >> PAGE_SHIFT);
|
|
if (r) {
|
|
DRM_ERROR("Failed initializing gws heap.\n");
|
|
return r;
|
|
}
|
|
}
|
|
|
|
/* OA */
|
|
if (adev->gds.oa.total_size) {
|
|
r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_OA,
|
|
adev->gds.oa.total_size >> PAGE_SHIFT);
|
|
if (r) {
|
|
DRM_ERROR("Failed initializing oa heap.\n");
|
|
return r;
|
|
}
|
|
}
|
|
|
|
r = amdgpu_ttm_debugfs_init(adev);
|
|
if (r) {
|
|
DRM_ERROR("Failed to init debugfs\n");
|
|
return r;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
void amdgpu_ttm_fini(struct amdgpu_device *adev)
|
|
{
|
|
if (!adev->mman.initialized)
|
|
return;
|
|
|
|
amdgpu_ttm_debugfs_fini(adev);
|
|
amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, NULL);
|
|
amdgpu_fw_reserve_vram_fini(adev);
|
|
|
|
ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_VRAM);
|
|
ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_TT);
|
|
if (adev->gds.mem.total_size)
|
|
ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GDS);
|
|
if (adev->gds.gws.total_size)
|
|
ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GWS);
|
|
if (adev->gds.oa.total_size)
|
|
ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_OA);
|
|
ttm_bo_device_release(&adev->mman.bdev);
|
|
amdgpu_ttm_global_fini(adev);
|
|
adev->mman.initialized = false;
|
|
DRM_INFO("amdgpu: ttm finalized\n");
|
|
}
|
|
|
|
/* this should only be called at bootup or when userspace
|
|
* isn't running */
|
|
void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size)
|
|
{
|
|
struct ttm_mem_type_manager *man;
|
|
|
|
if (!adev->mman.initialized)
|
|
return;
|
|
|
|
man = &adev->mman.bdev.man[TTM_PL_VRAM];
|
|
/* this just adjusts TTM size idea, which sets lpfn to the correct value */
|
|
man->size = size >> PAGE_SHIFT;
|
|
}
|
|
|
|
int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma)
|
|
{
|
|
struct drm_file *file_priv;
|
|
struct amdgpu_device *adev;
|
|
|
|
if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET))
|
|
return -EINVAL;
|
|
|
|
file_priv = filp->private_data;
|
|
adev = file_priv->minor->dev->dev_private;
|
|
if (adev == NULL)
|
|
return -EINVAL;
|
|
|
|
return ttm_bo_mmap(filp, vma, &adev->mman.bdev);
|
|
}
|
|
|
|
static int amdgpu_map_buffer(struct ttm_buffer_object *bo,
|
|
struct ttm_mem_reg *mem, unsigned num_pages,
|
|
uint64_t offset, unsigned window,
|
|
struct amdgpu_ring *ring,
|
|
uint64_t *addr)
|
|
{
|
|
struct amdgpu_ttm_tt *gtt = (void *)bo->ttm;
|
|
struct amdgpu_device *adev = ring->adev;
|
|
struct ttm_tt *ttm = bo->ttm;
|
|
struct amdgpu_job *job;
|
|
unsigned num_dw, num_bytes;
|
|
dma_addr_t *dma_address;
|
|
struct dma_fence *fence;
|
|
uint64_t src_addr, dst_addr;
|
|
uint64_t flags;
|
|
int r;
|
|
|
|
BUG_ON(adev->mman.buffer_funcs->copy_max_bytes <
|
|
AMDGPU_GTT_MAX_TRANSFER_SIZE * 8);
|
|
|
|
*addr = adev->mc.gart_start;
|
|
*addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE *
|
|
AMDGPU_GPU_PAGE_SIZE;
|
|
|
|
num_dw = adev->mman.buffer_funcs->copy_num_dw;
|
|
while (num_dw & 0x7)
|
|
num_dw++;
|
|
|
|
num_bytes = num_pages * 8;
|
|
|
|
r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes, &job);
|
|
if (r)
|
|
return r;
|
|
|
|
src_addr = num_dw * 4;
|
|
src_addr += job->ibs[0].gpu_addr;
|
|
|
|
dst_addr = adev->gart.table_addr;
|
|
dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8;
|
|
amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr,
|
|
dst_addr, num_bytes);
|
|
|
|
amdgpu_ring_pad_ib(ring, &job->ibs[0]);
|
|
WARN_ON(job->ibs[0].length_dw > num_dw);
|
|
|
|
dma_address = >t->ttm.dma_address[offset >> PAGE_SHIFT];
|
|
flags = amdgpu_ttm_tt_pte_flags(adev, ttm, mem);
|
|
r = amdgpu_gart_map(adev, 0, num_pages, dma_address, flags,
|
|
&job->ibs[0].ptr[num_dw]);
|
|
if (r)
|
|
goto error_free;
|
|
|
|
r = amdgpu_job_submit(job, ring, &adev->mman.entity,
|
|
AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
|
|
if (r)
|
|
goto error_free;
|
|
|
|
dma_fence_put(fence);
|
|
|
|
return r;
|
|
|
|
error_free:
|
|
amdgpu_job_free(job);
|
|
return r;
|
|
}
|
|
|
|
int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
|
|
uint64_t dst_offset, uint32_t byte_count,
|
|
struct reservation_object *resv,
|
|
struct dma_fence **fence, bool direct_submit,
|
|
bool vm_needs_flush)
|
|
{
|
|
struct amdgpu_device *adev = ring->adev;
|
|
struct amdgpu_job *job;
|
|
|
|
uint32_t max_bytes;
|
|
unsigned num_loops, num_dw;
|
|
unsigned i;
|
|
int r;
|
|
|
|
max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
|
|
num_loops = DIV_ROUND_UP(byte_count, max_bytes);
|
|
num_dw = num_loops * adev->mman.buffer_funcs->copy_num_dw;
|
|
|
|
/* for IB padding */
|
|
while (num_dw & 0x7)
|
|
num_dw++;
|
|
|
|
r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
|
|
if (r)
|
|
return r;
|
|
|
|
job->vm_needs_flush = vm_needs_flush;
|
|
if (resv) {
|
|
r = amdgpu_sync_resv(adev, &job->sync, resv,
|
|
AMDGPU_FENCE_OWNER_UNDEFINED,
|
|
false);
|
|
if (r) {
|
|
DRM_ERROR("sync failed (%d).\n", r);
|
|
goto error_free;
|
|
}
|
|
}
|
|
|
|
for (i = 0; i < num_loops; i++) {
|
|
uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
|
|
|
|
amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
|
|
dst_offset, cur_size_in_bytes);
|
|
|
|
src_offset += cur_size_in_bytes;
|
|
dst_offset += cur_size_in_bytes;
|
|
byte_count -= cur_size_in_bytes;
|
|
}
|
|
|
|
amdgpu_ring_pad_ib(ring, &job->ibs[0]);
|
|
WARN_ON(job->ibs[0].length_dw > num_dw);
|
|
if (direct_submit) {
|
|
r = amdgpu_ib_schedule(ring, job->num_ibs, job->ibs,
|
|
NULL, fence);
|
|
job->fence = dma_fence_get(*fence);
|
|
if (r)
|
|
DRM_ERROR("Error scheduling IBs (%d)\n", r);
|
|
amdgpu_job_free(job);
|
|
} else {
|
|
r = amdgpu_job_submit(job, ring, &adev->mman.entity,
|
|
AMDGPU_FENCE_OWNER_UNDEFINED, fence);
|
|
if (r)
|
|
goto error_free;
|
|
}
|
|
|
|
return r;
|
|
|
|
error_free:
|
|
amdgpu_job_free(job);
|
|
return r;
|
|
}
|
|
|
|
int amdgpu_fill_buffer(struct amdgpu_bo *bo,
|
|
uint64_t src_data,
|
|
struct reservation_object *resv,
|
|
struct dma_fence **fence)
|
|
{
|
|
struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
|
|
uint32_t max_bytes = 8 *
|
|
adev->vm_manager.vm_pte_funcs->set_max_nums_pte_pde;
|
|
struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
|
|
|
|
struct drm_mm_node *mm_node;
|
|
unsigned long num_pages;
|
|
unsigned int num_loops, num_dw;
|
|
|
|
struct amdgpu_job *job;
|
|
int r;
|
|
|
|
if (!ring->ready) {
|
|
DRM_ERROR("Trying to clear memory with ring turned off.\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (bo->tbo.mem.mem_type == TTM_PL_TT) {
|
|
r = amdgpu_ttm_alloc_gart(&bo->tbo);
|
|
if (r)
|
|
return r;
|
|
}
|
|
|
|
num_pages = bo->tbo.num_pages;
|
|
mm_node = bo->tbo.mem.mm_node;
|
|
num_loops = 0;
|
|
while (num_pages) {
|
|
uint32_t byte_count = mm_node->size << PAGE_SHIFT;
|
|
|
|
num_loops += DIV_ROUND_UP(byte_count, max_bytes);
|
|
num_pages -= mm_node->size;
|
|
++mm_node;
|
|
}
|
|
|
|
/* num of dwords for each SDMA_OP_PTEPDE cmd */
|
|
num_dw = num_loops * adev->vm_manager.vm_pte_funcs->set_pte_pde_num_dw;
|
|
|
|
/* for IB padding */
|
|
num_dw += 64;
|
|
|
|
r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
|
|
if (r)
|
|
return r;
|
|
|
|
if (resv) {
|
|
r = amdgpu_sync_resv(adev, &job->sync, resv,
|
|
AMDGPU_FENCE_OWNER_UNDEFINED, false);
|
|
if (r) {
|
|
DRM_ERROR("sync failed (%d).\n", r);
|
|
goto error_free;
|
|
}
|
|
}
|
|
|
|
num_pages = bo->tbo.num_pages;
|
|
mm_node = bo->tbo.mem.mm_node;
|
|
|
|
while (num_pages) {
|
|
uint32_t byte_count = mm_node->size << PAGE_SHIFT;
|
|
uint64_t dst_addr;
|
|
|
|
WARN_ONCE(byte_count & 0x7, "size should be a multiple of 8");
|
|
|
|
dst_addr = amdgpu_mm_node_addr(&bo->tbo, mm_node, &bo->tbo.mem);
|
|
while (byte_count) {
|
|
uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
|
|
|
|
amdgpu_vm_set_pte_pde(adev, &job->ibs[0],
|
|
dst_addr, 0,
|
|
cur_size_in_bytes >> 3, 0,
|
|
src_data);
|
|
|
|
dst_addr += cur_size_in_bytes;
|
|
byte_count -= cur_size_in_bytes;
|
|
}
|
|
|
|
num_pages -= mm_node->size;
|
|
++mm_node;
|
|
}
|
|
|
|
amdgpu_ring_pad_ib(ring, &job->ibs[0]);
|
|
WARN_ON(job->ibs[0].length_dw > num_dw);
|
|
r = amdgpu_job_submit(job, ring, &adev->mman.entity,
|
|
AMDGPU_FENCE_OWNER_UNDEFINED, fence);
|
|
if (r)
|
|
goto error_free;
|
|
|
|
return 0;
|
|
|
|
error_free:
|
|
amdgpu_job_free(job);
|
|
return r;
|
|
}
|
|
|
|
#if defined(CONFIG_DEBUG_FS)
|
|
|
|
static int amdgpu_mm_dump_table(struct seq_file *m, void *data)
|
|
{
|
|
struct drm_info_node *node = (struct drm_info_node *)m->private;
|
|
unsigned ttm_pl = *(int *)node->info_ent->data;
|
|
struct drm_device *dev = node->minor->dev;
|
|
struct amdgpu_device *adev = dev->dev_private;
|
|
struct ttm_mem_type_manager *man = &adev->mman.bdev.man[ttm_pl];
|
|
struct drm_printer p = drm_seq_file_printer(m);
|
|
|
|
man->func->debug(man, &p);
|
|
return 0;
|
|
}
|
|
|
|
static int ttm_pl_vram = TTM_PL_VRAM;
|
|
static int ttm_pl_tt = TTM_PL_TT;
|
|
|
|
static const struct drm_info_list amdgpu_ttm_debugfs_list[] = {
|
|
{"amdgpu_vram_mm", amdgpu_mm_dump_table, 0, &ttm_pl_vram},
|
|
{"amdgpu_gtt_mm", amdgpu_mm_dump_table, 0, &ttm_pl_tt},
|
|
{"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL},
|
|
#ifdef CONFIG_SWIOTLB
|
|
{"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL}
|
|
#endif
|
|
};
|
|
|
|
static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
|
|
size_t size, loff_t *pos)
|
|
{
|
|
struct amdgpu_device *adev = file_inode(f)->i_private;
|
|
ssize_t result = 0;
|
|
int r;
|
|
|
|
if (size & 0x3 || *pos & 0x3)
|
|
return -EINVAL;
|
|
|
|
if (*pos >= adev->mc.mc_vram_size)
|
|
return -ENXIO;
|
|
|
|
while (size) {
|
|
unsigned long flags;
|
|
uint32_t value;
|
|
|
|
if (*pos >= adev->mc.mc_vram_size)
|
|
return result;
|
|
|
|
spin_lock_irqsave(&adev->mmio_idx_lock, flags);
|
|
WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
|
|
WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31);
|
|
value = RREG32_NO_KIQ(mmMM_DATA);
|
|
spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
|
|
|
|
r = put_user(value, (uint32_t *)buf);
|
|
if (r)
|
|
return r;
|
|
|
|
result += 4;
|
|
buf += 4;
|
|
*pos += 4;
|
|
size -= 4;
|
|
}
|
|
|
|
return result;
|
|
}
|
|
|
|
static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf,
|
|
size_t size, loff_t *pos)
|
|
{
|
|
struct amdgpu_device *adev = file_inode(f)->i_private;
|
|
ssize_t result = 0;
|
|
int r;
|
|
|
|
if (size & 0x3 || *pos & 0x3)
|
|
return -EINVAL;
|
|
|
|
if (*pos >= adev->mc.mc_vram_size)
|
|
return -ENXIO;
|
|
|
|
while (size) {
|
|
unsigned long flags;
|
|
uint32_t value;
|
|
|
|
if (*pos >= adev->mc.mc_vram_size)
|
|
return result;
|
|
|
|
r = get_user(value, (uint32_t *)buf);
|
|
if (r)
|
|
return r;
|
|
|
|
spin_lock_irqsave(&adev->mmio_idx_lock, flags);
|
|
WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
|
|
WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31);
|
|
WREG32_NO_KIQ(mmMM_DATA, value);
|
|
spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
|
|
|
|
result += 4;
|
|
buf += 4;
|
|
*pos += 4;
|
|
size -= 4;
|
|
}
|
|
|
|
return result;
|
|
}
|
|
|
|
static const struct file_operations amdgpu_ttm_vram_fops = {
|
|
.owner = THIS_MODULE,
|
|
.read = amdgpu_ttm_vram_read,
|
|
.write = amdgpu_ttm_vram_write,
|
|
.llseek = default_llseek,
|
|
};
|
|
|
|
#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
|
|
|
|
static ssize_t amdgpu_ttm_gtt_read(struct file *f, char __user *buf,
|
|
size_t size, loff_t *pos)
|
|
{
|
|
struct amdgpu_device *adev = file_inode(f)->i_private;
|
|
ssize_t result = 0;
|
|
int r;
|
|
|
|
while (size) {
|
|
loff_t p = *pos / PAGE_SIZE;
|
|
unsigned off = *pos & ~PAGE_MASK;
|
|
size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
|
|
struct page *page;
|
|
void *ptr;
|
|
|
|
if (p >= adev->gart.num_cpu_pages)
|
|
return result;
|
|
|
|
page = adev->gart.pages[p];
|
|
if (page) {
|
|
ptr = kmap(page);
|
|
ptr += off;
|
|
|
|
r = copy_to_user(buf, ptr, cur_size);
|
|
kunmap(adev->gart.pages[p]);
|
|
} else
|
|
r = clear_user(buf, cur_size);
|
|
|
|
if (r)
|
|
return -EFAULT;
|
|
|
|
result += cur_size;
|
|
buf += cur_size;
|
|
*pos += cur_size;
|
|
size -= cur_size;
|
|
}
|
|
|
|
return result;
|
|
}
|
|
|
|
static const struct file_operations amdgpu_ttm_gtt_fops = {
|
|
.owner = THIS_MODULE,
|
|
.read = amdgpu_ttm_gtt_read,
|
|
.llseek = default_llseek
|
|
};
|
|
|
|
#endif
|
|
|
|
static ssize_t amdgpu_iova_to_phys_read(struct file *f, char __user *buf,
|
|
size_t size, loff_t *pos)
|
|
{
|
|
struct amdgpu_device *adev = file_inode(f)->i_private;
|
|
int r;
|
|
uint64_t phys;
|
|
struct iommu_domain *dom;
|
|
|
|
// always return 8 bytes
|
|
if (size != 8)
|
|
return -EINVAL;
|
|
|
|
// only accept page addresses
|
|
if (*pos & 0xFFF)
|
|
return -EINVAL;
|
|
|
|
dom = iommu_get_domain_for_dev(adev->dev);
|
|
if (dom)
|
|
phys = iommu_iova_to_phys(dom, *pos);
|
|
else
|
|
phys = *pos;
|
|
|
|
r = copy_to_user(buf, &phys, 8);
|
|
if (r)
|
|
return -EFAULT;
|
|
|
|
return 8;
|
|
}
|
|
|
|
static const struct file_operations amdgpu_ttm_iova_fops = {
|
|
.owner = THIS_MODULE,
|
|
.read = amdgpu_iova_to_phys_read,
|
|
.llseek = default_llseek
|
|
};
|
|
|
|
static const struct {
|
|
char *name;
|
|
const struct file_operations *fops;
|
|
int domain;
|
|
} ttm_debugfs_entries[] = {
|
|
{ "amdgpu_vram", &amdgpu_ttm_vram_fops, TTM_PL_VRAM },
|
|
#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
|
|
{ "amdgpu_gtt", &amdgpu_ttm_gtt_fops, TTM_PL_TT },
|
|
#endif
|
|
{ "amdgpu_iova", &amdgpu_ttm_iova_fops, TTM_PL_SYSTEM },
|
|
};
|
|
|
|
#endif
|
|
|
|
static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
|
|
{
|
|
#if defined(CONFIG_DEBUG_FS)
|
|
unsigned count;
|
|
|
|
struct drm_minor *minor = adev->ddev->primary;
|
|
struct dentry *ent, *root = minor->debugfs_root;
|
|
|
|
for (count = 0; count < ARRAY_SIZE(ttm_debugfs_entries); count++) {
|
|
ent = debugfs_create_file(
|
|
ttm_debugfs_entries[count].name,
|
|
S_IFREG | S_IRUGO, root,
|
|
adev,
|
|
ttm_debugfs_entries[count].fops);
|
|
if (IS_ERR(ent))
|
|
return PTR_ERR(ent);
|
|
if (ttm_debugfs_entries[count].domain == TTM_PL_VRAM)
|
|
i_size_write(ent->d_inode, adev->mc.mc_vram_size);
|
|
else if (ttm_debugfs_entries[count].domain == TTM_PL_TT)
|
|
i_size_write(ent->d_inode, adev->mc.gart_size);
|
|
adev->mman.debugfs_entries[count] = ent;
|
|
}
|
|
|
|
count = ARRAY_SIZE(amdgpu_ttm_debugfs_list);
|
|
|
|
#ifdef CONFIG_SWIOTLB
|
|
if (!swiotlb_nr_tbl())
|
|
--count;
|
|
#endif
|
|
|
|
return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count);
|
|
#else
|
|
return 0;
|
|
#endif
|
|
}
|
|
|
|
static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev)
|
|
{
|
|
#if defined(CONFIG_DEBUG_FS)
|
|
unsigned i;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(ttm_debugfs_entries); i++)
|
|
debugfs_remove(adev->mman.debugfs_entries[i]);
|
|
#endif
|
|
}
|