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58c84eda07
If we fail to assign resources to a PCI BAR, this patch makes us try the original address from BIOS rather than leaving it disabled. Linux tries to make sure all PCI device BARs are inside the upstream PCI host bridge or P2P bridge apertures, reassigning BARs if necessary. Windows does similar reassignment. Before this patch, if we could not move a BAR into an aperture, we left the resource unassigned, i.e., at address zero. Windows leaves such BARs at the original BIOS addresses, and this patch makes Linux do the same. This is a bit ugly because we disable the resource long before we try to reassign it, so we have to keep track of the BIOS BAR address somewhere. For lack of a better place, I put it in the struct pci_dev. I think it would be cleaner to attempt the assignment immediately when the claim fails, so we could easily remember the original address. But we currently claim motherboard resources in the middle, after attempting to claim PCI resources and before assigning new PCI resources, and changing that is a fairly big job. Addresses https://bugzilla.kernel.org/show_bug.cgi?id=16263 Reported-by: Andrew <nitr0@seti.kr.ua> Tested-by: Andrew <nitr0@seti.kr.ua> Signed-off-by: Bjorn Helgaas <bjorn.helgaas@hp.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
325 lines
8.8 KiB
C
325 lines
8.8 KiB
C
/*
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* Low-Level PCI Access for i386 machines
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*
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* Copyright 1993, 1994 Drew Eckhardt
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* Visionary Computing
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* (Unix and Linux consulting and custom programming)
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* Drew@Colorado.EDU
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* +1 (303) 786-7975
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*
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* Drew's work was sponsored by:
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* iX Multiuser Multitasking Magazine
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* Hannover, Germany
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* hm@ix.de
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*
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* Copyright 1997--2000 Martin Mares <mj@ucw.cz>
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*
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* For more information, please consult the following manuals (look at
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* http://www.pcisig.com/ for how to get them):
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*
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* PCI BIOS Specification
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* PCI Local Bus Specification
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* PCI to PCI Bridge Specification
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* PCI System Design Guide
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*
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*/
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/ioport.h>
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#include <linux/errno.h>
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#include <linux/bootmem.h>
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#include <asm/pat.h>
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#include <asm/e820.h>
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#include <asm/pci_x86.h>
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#include <asm/io_apic.h>
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static int
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skip_isa_ioresource_align(struct pci_dev *dev) {
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if ((pci_probe & PCI_CAN_SKIP_ISA_ALIGN) &&
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!(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA))
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return 1;
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return 0;
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}
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/*
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* We need to avoid collisions with `mirrored' VGA ports
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* and other strange ISA hardware, so we always want the
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* addresses to be allocated in the 0x000-0x0ff region
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* modulo 0x400.
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*
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* Why? Because some silly external IO cards only decode
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* the low 10 bits of the IO address. The 0x00-0xff region
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* is reserved for motherboard devices that decode all 16
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* bits, so it's ok to allocate at, say, 0x2800-0x28ff,
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* but we want to try to avoid allocating at 0x2900-0x2bff
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* which might have be mirrored at 0x0100-0x03ff..
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*/
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resource_size_t
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pcibios_align_resource(void *data, const struct resource *res,
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resource_size_t size, resource_size_t align)
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{
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struct pci_dev *dev = data;
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resource_size_t start = res->start;
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if (res->flags & IORESOURCE_IO) {
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if (skip_isa_ioresource_align(dev))
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return start;
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if (start & 0x300)
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start = (start + 0x3ff) & ~0x3ff;
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} else if (res->flags & IORESOURCE_MEM) {
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if (start < BIOS_END)
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start = BIOS_END;
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}
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return start;
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}
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EXPORT_SYMBOL(pcibios_align_resource);
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/*
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* Handle resources of PCI devices. If the world were perfect, we could
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* just allocate all the resource regions and do nothing more. It isn't.
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* On the other hand, we cannot just re-allocate all devices, as it would
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* require us to know lots of host bridge internals. So we attempt to
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* keep as much of the original configuration as possible, but tweak it
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* when it's found to be wrong.
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*
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* Known BIOS problems we have to work around:
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* - I/O or memory regions not configured
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* - regions configured, but not enabled in the command register
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* - bogus I/O addresses above 64K used
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* - expansion ROMs left enabled (this may sound harmless, but given
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* the fact the PCI specs explicitly allow address decoders to be
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* shared between expansion ROMs and other resource regions, it's
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* at least dangerous)
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* - bad resource sizes or overlaps with other regions
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*
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* Our solution:
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* (1) Allocate resources for all buses behind PCI-to-PCI bridges.
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* This gives us fixed barriers on where we can allocate.
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* (2) Allocate resources for all enabled devices. If there is
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* a collision, just mark the resource as unallocated. Also
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* disable expansion ROMs during this step.
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* (3) Try to allocate resources for disabled devices. If the
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* resources were assigned correctly, everything goes well,
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* if they weren't, they won't disturb allocation of other
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* resources.
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* (4) Assign new addresses to resources which were either
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* not configured at all or misconfigured. If explicitly
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* requested by the user, configure expansion ROM address
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* as well.
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*/
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static void __init pcibios_allocate_bus_resources(struct list_head *bus_list)
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{
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struct pci_bus *bus;
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struct pci_dev *dev;
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int idx;
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struct resource *r;
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/* Depth-First Search on bus tree */
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list_for_each_entry(bus, bus_list, node) {
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if ((dev = bus->self)) {
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for (idx = PCI_BRIDGE_RESOURCES;
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idx < PCI_NUM_RESOURCES; idx++) {
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r = &dev->resource[idx];
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if (!r->flags)
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continue;
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if (!r->start ||
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pci_claim_resource(dev, idx) < 0) {
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/*
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* Something is wrong with the region.
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* Invalidate the resource to prevent
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* child resource allocations in this
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* range.
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*/
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r->start = r->end = 0;
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r->flags = 0;
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}
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}
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}
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pcibios_allocate_bus_resources(&bus->children);
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}
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}
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struct pci_check_idx_range {
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int start;
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int end;
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};
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static void __init pcibios_allocate_resources(int pass)
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{
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struct pci_dev *dev = NULL;
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int idx, disabled, i;
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u16 command;
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struct resource *r;
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struct pci_check_idx_range idx_range[] = {
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{ PCI_STD_RESOURCES, PCI_STD_RESOURCE_END },
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#ifdef CONFIG_PCI_IOV
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{ PCI_IOV_RESOURCES, PCI_IOV_RESOURCE_END },
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#endif
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};
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for_each_pci_dev(dev) {
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pci_read_config_word(dev, PCI_COMMAND, &command);
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for (i = 0; i < ARRAY_SIZE(idx_range); i++)
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for (idx = idx_range[i].start; idx <= idx_range[i].end; idx++) {
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r = &dev->resource[idx];
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if (r->parent) /* Already allocated */
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continue;
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if (!r->start) /* Address not assigned at all */
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continue;
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if (r->flags & IORESOURCE_IO)
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disabled = !(command & PCI_COMMAND_IO);
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else
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disabled = !(command & PCI_COMMAND_MEMORY);
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if (pass == disabled) {
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dev_dbg(&dev->dev,
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"BAR %d: reserving %pr (d=%d, p=%d)\n",
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idx, r, disabled, pass);
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if (pci_claim_resource(dev, idx) < 0) {
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/* We'll assign a new address later */
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dev->fw_addr[idx] = r->start;
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r->end -= r->start;
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r->start = 0;
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}
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}
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}
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if (!pass) {
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r = &dev->resource[PCI_ROM_RESOURCE];
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if (r->flags & IORESOURCE_ROM_ENABLE) {
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/* Turn the ROM off, leave the resource region,
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* but keep it unregistered. */
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u32 reg;
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dev_dbg(&dev->dev, "disabling ROM %pR\n", r);
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r->flags &= ~IORESOURCE_ROM_ENABLE;
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pci_read_config_dword(dev,
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dev->rom_base_reg, ®);
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pci_write_config_dword(dev, dev->rom_base_reg,
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reg & ~PCI_ROM_ADDRESS_ENABLE);
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}
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}
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}
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}
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static int __init pcibios_assign_resources(void)
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{
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struct pci_dev *dev = NULL;
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struct resource *r;
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if (!(pci_probe & PCI_ASSIGN_ROMS)) {
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/*
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* Try to use BIOS settings for ROMs, otherwise let
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* pci_assign_unassigned_resources() allocate the new
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* addresses.
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*/
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for_each_pci_dev(dev) {
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r = &dev->resource[PCI_ROM_RESOURCE];
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if (!r->flags || !r->start)
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continue;
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if (pci_claim_resource(dev, PCI_ROM_RESOURCE) < 0) {
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r->end -= r->start;
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r->start = 0;
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}
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}
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}
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pci_assign_unassigned_resources();
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return 0;
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}
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void __init pcibios_resource_survey(void)
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{
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DBG("PCI: Allocating resources\n");
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pcibios_allocate_bus_resources(&pci_root_buses);
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pcibios_allocate_resources(0);
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pcibios_allocate_resources(1);
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e820_reserve_resources_late();
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/*
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* Insert the IO APIC resources after PCI initialization has
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* occured to handle IO APICS that are mapped in on a BAR in
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* PCI space, but before trying to assign unassigned pci res.
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*/
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ioapic_insert_resources();
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}
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/**
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* called in fs_initcall (one below subsys_initcall),
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* give a chance for motherboard reserve resources
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*/
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fs_initcall(pcibios_assign_resources);
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/*
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* If we set up a device for bus mastering, we need to check the latency
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* timer as certain crappy BIOSes forget to set it properly.
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*/
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unsigned int pcibios_max_latency = 255;
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void pcibios_set_master(struct pci_dev *dev)
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{
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u8 lat;
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pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
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if (lat < 16)
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lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
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else if (lat > pcibios_max_latency)
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lat = pcibios_max_latency;
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else
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return;
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dev_printk(KERN_DEBUG, &dev->dev, "setting latency timer to %d\n", lat);
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pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
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}
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static const struct vm_operations_struct pci_mmap_ops = {
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.access = generic_access_phys,
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};
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int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
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enum pci_mmap_state mmap_state, int write_combine)
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{
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unsigned long prot;
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/* I/O space cannot be accessed via normal processor loads and
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* stores on this platform.
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*/
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if (mmap_state == pci_mmap_io)
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return -EINVAL;
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prot = pgprot_val(vma->vm_page_prot);
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/*
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* Return error if pat is not enabled and write_combine is requested.
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* Caller can followup with UC MINUS request and add a WC mtrr if there
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* is a free mtrr slot.
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*/
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if (!pat_enabled && write_combine)
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return -EINVAL;
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if (pat_enabled && write_combine)
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prot |= _PAGE_CACHE_WC;
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else if (pat_enabled || boot_cpu_data.x86 > 3)
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/*
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* ioremap() and ioremap_nocache() defaults to UC MINUS for now.
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* To avoid attribute conflicts, request UC MINUS here
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* aswell.
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*/
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prot |= _PAGE_CACHE_UC_MINUS;
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vma->vm_page_prot = __pgprot(prot);
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if (io_remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
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vma->vm_end - vma->vm_start,
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vma->vm_page_prot))
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return -EAGAIN;
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vma->vm_ops = &pci_mmap_ops;
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return 0;
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}
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