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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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056f6c8702
If CONFIG_SH_DMAE_BASE (which is required for DMA engine support for
legacy SH, SH/R-Mobile, and R-Car Gen1, but not for R-Car Gen2) is not
enabled, but CONFIG_RCAR_DMAC (for R-Car Gen2 DMA engine support) is,
and the DTS doesn't provide a "dmas" property for a device,
dma_request_slave_channel_compat() incorrectly succeeds, and returns a
DMA channel.
However, when trying to use that DMA channel later, it fails with:
rcar-dmac e6700000.dma-controller: rcar_dmac_prep_slave_sg: bad parameter: len=1, id=-22
(Fortunately most drivers can handle this failure, and fall back to
PIO)
The reason for this is that a NULL legacy filter function is used, which
actually means "all channels are OK", not "do not match".
If CONFIG_SH_DMAE_BASE is enabled (like in shmobile_defconfig, which
supports other SoCs besides R-Car Gen2), shdma_chan_filter() correctly
returns false, as no available channel on R-Car Gen2 matches a
shdma-base channel.
If the DTS does provide a "dmas" property, dma_request_slave_channel()
succeeds, and legacy filter-based matching is not used.
To fix this, change shdma_chan_filter from being NULL to a dummy
function that always returns false, like is done on other platforms.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
138 lines
4.4 KiB
C
138 lines
4.4 KiB
C
/*
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* Dmaengine driver base library for DMA controllers, found on SH-based SoCs
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*
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* extracted from shdma.c and headers
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*
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* Copyright (C) 2011-2012 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
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* Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
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* Copyright (C) 2009 Renesas Solutions, Inc. All rights reserved.
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* Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
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*
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* This is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*/
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#ifndef SHDMA_BASE_H
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#define SHDMA_BASE_H
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#include <linux/dmaengine.h>
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#include <linux/interrupt.h>
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#include <linux/list.h>
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#include <linux/types.h>
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/**
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* shdma_pm_state - DMA channel PM state
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* SHDMA_PM_ESTABLISHED: either idle or during data transfer
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* SHDMA_PM_BUSY: during the transfer preparation, when we have to
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* drop the lock temporarily
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* SHDMA_PM_PENDING: transfers pending
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*/
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enum shdma_pm_state {
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SHDMA_PM_ESTABLISHED,
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SHDMA_PM_BUSY,
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SHDMA_PM_PENDING,
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};
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struct device;
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/*
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* Drivers, using this library are expected to embed struct shdma_dev,
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* struct shdma_chan, struct shdma_desc, and struct shdma_slave
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* in their respective device, channel, descriptor and slave objects.
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*/
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struct shdma_slave {
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int slave_id;
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};
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struct shdma_desc {
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struct list_head node;
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struct dma_async_tx_descriptor async_tx;
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enum dma_transfer_direction direction;
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size_t partial;
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dma_cookie_t cookie;
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int chunks;
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int mark;
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bool cyclic; /* used as cyclic transfer */
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};
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struct shdma_chan {
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spinlock_t chan_lock; /* Channel operation lock */
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struct list_head ld_queue; /* Link descriptors queue */
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struct list_head ld_free; /* Free link descriptors */
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struct dma_chan dma_chan; /* DMA channel */
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struct device *dev; /* Channel device */
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void *desc; /* buffer for descriptor array */
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int desc_num; /* desc count */
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size_t max_xfer_len; /* max transfer length */
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int id; /* Raw id of this channel */
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int irq; /* Channel IRQ */
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int slave_id; /* Client ID for slave DMA */
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int real_slave_id; /* argument passed to filter function */
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int hw_req; /* DMA request line for slave DMA - same
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* as MID/RID, used with DT */
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enum shdma_pm_state pm_state;
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};
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/**
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* struct shdma_ops - simple DMA driver operations
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* desc_completed: return true, if this is the descriptor, that just has
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* completed (atomic)
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* halt_channel: stop DMA channel operation (atomic)
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* channel_busy: return true, if the channel is busy (atomic)
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* slave_addr: return slave DMA address
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* desc_setup: set up the hardware specific descriptor portion (atomic)
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* set_slave: bind channel to a slave
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* setup_xfer: configure channel hardware for operation (atomic)
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* start_xfer: start the DMA transfer (atomic)
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* embedded_desc: return Nth struct shdma_desc pointer from the
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* descriptor array
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* chan_irq: process channel IRQ, return true if a transfer has
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* completed (atomic)
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*/
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struct shdma_ops {
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bool (*desc_completed)(struct shdma_chan *, struct shdma_desc *);
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void (*halt_channel)(struct shdma_chan *);
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bool (*channel_busy)(struct shdma_chan *);
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dma_addr_t (*slave_addr)(struct shdma_chan *);
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int (*desc_setup)(struct shdma_chan *, struct shdma_desc *,
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dma_addr_t, dma_addr_t, size_t *);
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int (*set_slave)(struct shdma_chan *, int, dma_addr_t, bool);
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void (*setup_xfer)(struct shdma_chan *, int);
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void (*start_xfer)(struct shdma_chan *, struct shdma_desc *);
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struct shdma_desc *(*embedded_desc)(void *, int);
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bool (*chan_irq)(struct shdma_chan *, int);
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size_t (*get_partial)(struct shdma_chan *, struct shdma_desc *);
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};
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struct shdma_dev {
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struct dma_device dma_dev;
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struct shdma_chan **schan;
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const struct shdma_ops *ops;
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size_t desc_size;
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};
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#define shdma_for_each_chan(c, d, i) for (i = 0, c = (d)->schan[0]; \
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i < (d)->dma_dev.chancnt; c = (d)->schan[++i])
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int shdma_request_irq(struct shdma_chan *, int,
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unsigned long, const char *);
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bool shdma_reset(struct shdma_dev *sdev);
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void shdma_chan_probe(struct shdma_dev *sdev,
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struct shdma_chan *schan, int id);
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void shdma_chan_remove(struct shdma_chan *schan);
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int shdma_init(struct device *dev, struct shdma_dev *sdev,
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int chan_num);
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void shdma_cleanup(struct shdma_dev *sdev);
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#if IS_ENABLED(CONFIG_SH_DMAE_BASE)
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bool shdma_chan_filter(struct dma_chan *chan, void *arg);
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#else
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static inline bool shdma_chan_filter(struct dma_chan *chan, void *arg)
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{
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return false;
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}
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#endif
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#endif
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