mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-21 12:49:08 +07:00
afedb4b728
Fix the following sparse warning: drivers/spi/spi-mtk-nor.c:394:5: warning: symbol 'mtk_nor_exec_op' was not declared. Should it be static? Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Jason Yan <yanaijie@huawei.com> Link: https://lore.kernel.org/r/20200409085009.44971-1-yanaijie@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
690 lines
17 KiB
C
690 lines
17 KiB
C
// SPDX-License-Identifier: GPL-2.0
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//
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// Mediatek SPI NOR controller driver
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//
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// Copyright (C) 2020 Chuanhong Guo <gch981213@gmail.com>
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#include <linux/bits.h>
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#include <linux/clk.h>
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#include <linux/completion.h>
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#include <linux/dma-mapping.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/spi/spi.h>
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#include <linux/spi/spi-mem.h>
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#include <linux/string.h>
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#define DRIVER_NAME "mtk-spi-nor"
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#define MTK_NOR_REG_CMD 0x00
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#define MTK_NOR_CMD_WRITE BIT(4)
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#define MTK_NOR_CMD_PROGRAM BIT(2)
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#define MTK_NOR_CMD_READ BIT(0)
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#define MTK_NOR_CMD_MASK GENMASK(5, 0)
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#define MTK_NOR_REG_PRG_CNT 0x04
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#define MTK_NOR_REG_RDATA 0x0c
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#define MTK_NOR_REG_RADR0 0x10
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#define MTK_NOR_REG_RADR(n) (MTK_NOR_REG_RADR0 + 4 * (n))
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#define MTK_NOR_REG_RADR3 0xc8
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#define MTK_NOR_REG_WDATA 0x1c
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#define MTK_NOR_REG_PRGDATA0 0x20
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#define MTK_NOR_REG_PRGDATA(n) (MTK_NOR_REG_PRGDATA0 + 4 * (n))
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#define MTK_NOR_REG_PRGDATA_MAX 5
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#define MTK_NOR_REG_SHIFT0 0x38
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#define MTK_NOR_REG_SHIFT(n) (MTK_NOR_REG_SHIFT0 + 4 * (n))
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#define MTK_NOR_REG_SHIFT_MAX 9
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#define MTK_NOR_REG_CFG1 0x60
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#define MTK_NOR_FAST_READ BIT(0)
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#define MTK_NOR_REG_CFG2 0x64
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#define MTK_NOR_WR_CUSTOM_OP_EN BIT(4)
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#define MTK_NOR_WR_BUF_EN BIT(0)
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#define MTK_NOR_REG_PP_DATA 0x98
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#define MTK_NOR_REG_IRQ_STAT 0xa8
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#define MTK_NOR_REG_IRQ_EN 0xac
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#define MTK_NOR_IRQ_DMA BIT(7)
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#define MTK_NOR_IRQ_MASK GENMASK(7, 0)
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#define MTK_NOR_REG_CFG3 0xb4
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#define MTK_NOR_DISABLE_WREN BIT(7)
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#define MTK_NOR_DISABLE_SR_POLL BIT(5)
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#define MTK_NOR_REG_WP 0xc4
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#define MTK_NOR_ENABLE_SF_CMD 0x30
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#define MTK_NOR_REG_BUSCFG 0xcc
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#define MTK_NOR_4B_ADDR BIT(4)
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#define MTK_NOR_QUAD_ADDR BIT(3)
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#define MTK_NOR_QUAD_READ BIT(2)
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#define MTK_NOR_DUAL_ADDR BIT(1)
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#define MTK_NOR_DUAL_READ BIT(0)
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#define MTK_NOR_BUS_MODE_MASK GENMASK(4, 0)
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#define MTK_NOR_REG_DMA_CTL 0x718
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#define MTK_NOR_DMA_START BIT(0)
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#define MTK_NOR_REG_DMA_FADR 0x71c
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#define MTK_NOR_REG_DMA_DADR 0x720
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#define MTK_NOR_REG_DMA_END_DADR 0x724
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#define MTK_NOR_PRG_MAX_SIZE 6
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// Reading DMA src/dst addresses have to be 16-byte aligned
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#define MTK_NOR_DMA_ALIGN 16
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#define MTK_NOR_DMA_ALIGN_MASK (MTK_NOR_DMA_ALIGN - 1)
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// and we allocate a bounce buffer if destination address isn't aligned.
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#define MTK_NOR_BOUNCE_BUF_SIZE PAGE_SIZE
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// Buffered page program can do one 128-byte transfer
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#define MTK_NOR_PP_SIZE 128
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#define CLK_TO_US(sp, clkcnt) ((clkcnt) * 1000000 / sp->spi_freq)
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struct mtk_nor {
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struct spi_controller *ctlr;
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struct device *dev;
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void __iomem *base;
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u8 *buffer;
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struct clk *spi_clk;
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struct clk *ctlr_clk;
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unsigned int spi_freq;
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bool wbuf_en;
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bool has_irq;
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struct completion op_done;
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};
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static inline void mtk_nor_rmw(struct mtk_nor *sp, u32 reg, u32 set, u32 clr)
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{
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u32 val = readl(sp->base + reg);
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val &= ~clr;
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val |= set;
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writel(val, sp->base + reg);
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}
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static inline int mtk_nor_cmd_exec(struct mtk_nor *sp, u32 cmd, ulong clk)
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{
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ulong delay = CLK_TO_US(sp, clk);
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u32 reg;
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int ret;
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writel(cmd, sp->base + MTK_NOR_REG_CMD);
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ret = readl_poll_timeout(sp->base + MTK_NOR_REG_CMD, reg, !(reg & cmd),
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delay / 3, (delay + 1) * 200);
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if (ret < 0)
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dev_err(sp->dev, "command %u timeout.\n", cmd);
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return ret;
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}
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static void mtk_nor_set_addr(struct mtk_nor *sp, const struct spi_mem_op *op)
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{
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u32 addr = op->addr.val;
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int i;
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for (i = 0; i < 3; i++) {
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writeb(addr & 0xff, sp->base + MTK_NOR_REG_RADR(i));
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addr >>= 8;
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}
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if (op->addr.nbytes == 4) {
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writeb(addr & 0xff, sp->base + MTK_NOR_REG_RADR3);
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mtk_nor_rmw(sp, MTK_NOR_REG_BUSCFG, MTK_NOR_4B_ADDR, 0);
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} else {
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mtk_nor_rmw(sp, MTK_NOR_REG_BUSCFG, 0, MTK_NOR_4B_ADDR);
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}
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}
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static bool mtk_nor_match_read(const struct spi_mem_op *op)
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{
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int dummy = 0;
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if (op->dummy.buswidth)
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dummy = op->dummy.nbytes * BITS_PER_BYTE / op->dummy.buswidth;
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if ((op->data.buswidth == 2) || (op->data.buswidth == 4)) {
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if (op->addr.buswidth == 1)
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return dummy == 8;
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else if (op->addr.buswidth == 2)
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return dummy == 4;
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else if (op->addr.buswidth == 4)
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return dummy == 6;
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} else if ((op->addr.buswidth == 1) && (op->data.buswidth == 1)) {
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if (op->cmd.opcode == 0x03)
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return dummy == 0;
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else if (op->cmd.opcode == 0x0b)
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return dummy == 8;
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}
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return false;
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}
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static int mtk_nor_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op)
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{
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size_t len;
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if (!op->data.nbytes)
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return 0;
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if ((op->addr.nbytes == 3) || (op->addr.nbytes == 4)) {
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if ((op->data.dir == SPI_MEM_DATA_IN) &&
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mtk_nor_match_read(op)) {
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if ((op->addr.val & MTK_NOR_DMA_ALIGN_MASK) ||
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(op->data.nbytes < MTK_NOR_DMA_ALIGN))
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op->data.nbytes = 1;
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else if (!((ulong)(op->data.buf.in) &
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MTK_NOR_DMA_ALIGN_MASK))
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op->data.nbytes &= ~MTK_NOR_DMA_ALIGN_MASK;
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else if (op->data.nbytes > MTK_NOR_BOUNCE_BUF_SIZE)
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op->data.nbytes = MTK_NOR_BOUNCE_BUF_SIZE;
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return 0;
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} else if (op->data.dir == SPI_MEM_DATA_OUT) {
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if (op->data.nbytes >= MTK_NOR_PP_SIZE)
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op->data.nbytes = MTK_NOR_PP_SIZE;
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else
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op->data.nbytes = 1;
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return 0;
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}
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}
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len = MTK_NOR_PRG_MAX_SIZE - sizeof(op->cmd.opcode) - op->addr.nbytes -
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op->dummy.nbytes;
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if (op->data.nbytes > len)
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op->data.nbytes = len;
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return 0;
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}
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static bool mtk_nor_supports_op(struct spi_mem *mem,
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const struct spi_mem_op *op)
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{
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size_t len;
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if (op->cmd.buswidth != 1)
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return false;
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if ((op->addr.nbytes == 3) || (op->addr.nbytes == 4)) {
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if ((op->data.dir == SPI_MEM_DATA_IN) && mtk_nor_match_read(op))
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return true;
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else if (op->data.dir == SPI_MEM_DATA_OUT)
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return (op->addr.buswidth == 1) &&
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(op->dummy.buswidth == 0) &&
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(op->data.buswidth == 1);
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}
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len = sizeof(op->cmd.opcode) + op->addr.nbytes + op->dummy.nbytes;
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if ((len > MTK_NOR_PRG_MAX_SIZE) ||
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((op->data.nbytes) && (len == MTK_NOR_PRG_MAX_SIZE)))
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return false;
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return true;
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}
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static void mtk_nor_setup_bus(struct mtk_nor *sp, const struct spi_mem_op *op)
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{
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u32 reg = 0;
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if (op->addr.nbytes == 4)
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reg |= MTK_NOR_4B_ADDR;
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if (op->data.buswidth == 4) {
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reg |= MTK_NOR_QUAD_READ;
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writeb(op->cmd.opcode, sp->base + MTK_NOR_REG_PRGDATA(4));
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if (op->addr.buswidth == 4)
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reg |= MTK_NOR_QUAD_ADDR;
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} else if (op->data.buswidth == 2) {
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reg |= MTK_NOR_DUAL_READ;
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writeb(op->cmd.opcode, sp->base + MTK_NOR_REG_PRGDATA(3));
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if (op->addr.buswidth == 2)
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reg |= MTK_NOR_DUAL_ADDR;
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} else {
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if (op->cmd.opcode == 0x0b)
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mtk_nor_rmw(sp, MTK_NOR_REG_CFG1, MTK_NOR_FAST_READ, 0);
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else
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mtk_nor_rmw(sp, MTK_NOR_REG_CFG1, 0, MTK_NOR_FAST_READ);
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}
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mtk_nor_rmw(sp, MTK_NOR_REG_BUSCFG, reg, MTK_NOR_BUS_MODE_MASK);
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}
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static int mtk_nor_read_dma(struct mtk_nor *sp, u32 from, unsigned int length,
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u8 *buffer)
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{
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int ret = 0;
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ulong delay;
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u32 reg;
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dma_addr_t dma_addr;
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dma_addr = dma_map_single(sp->dev, buffer, length, DMA_FROM_DEVICE);
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if (dma_mapping_error(sp->dev, dma_addr)) {
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dev_err(sp->dev, "failed to map dma buffer.\n");
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return -EINVAL;
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}
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writel(from, sp->base + MTK_NOR_REG_DMA_FADR);
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writel(dma_addr, sp->base + MTK_NOR_REG_DMA_DADR);
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writel(dma_addr + length, sp->base + MTK_NOR_REG_DMA_END_DADR);
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if (sp->has_irq) {
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reinit_completion(&sp->op_done);
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mtk_nor_rmw(sp, MTK_NOR_REG_IRQ_EN, MTK_NOR_IRQ_DMA, 0);
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}
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mtk_nor_rmw(sp, MTK_NOR_REG_DMA_CTL, MTK_NOR_DMA_START, 0);
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delay = CLK_TO_US(sp, (length + 5) * BITS_PER_BYTE);
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if (sp->has_irq) {
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if (!wait_for_completion_timeout(&sp->op_done,
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(delay + 1) * 100))
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ret = -ETIMEDOUT;
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} else {
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ret = readl_poll_timeout(sp->base + MTK_NOR_REG_DMA_CTL, reg,
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!(reg & MTK_NOR_DMA_START), delay / 3,
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(delay + 1) * 100);
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}
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dma_unmap_single(sp->dev, dma_addr, length, DMA_FROM_DEVICE);
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if (ret < 0)
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dev_err(sp->dev, "dma read timeout.\n");
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return ret;
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}
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static int mtk_nor_read_bounce(struct mtk_nor *sp, u32 from,
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unsigned int length, u8 *buffer)
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{
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unsigned int rdlen;
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int ret;
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if (length & MTK_NOR_DMA_ALIGN_MASK)
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rdlen = (length + MTK_NOR_DMA_ALIGN) & ~MTK_NOR_DMA_ALIGN_MASK;
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else
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rdlen = length;
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ret = mtk_nor_read_dma(sp, from, rdlen, sp->buffer);
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if (ret)
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return ret;
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memcpy(buffer, sp->buffer, length);
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return 0;
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}
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static int mtk_nor_read_pio(struct mtk_nor *sp, const struct spi_mem_op *op)
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{
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u8 *buf = op->data.buf.in;
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int ret;
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ret = mtk_nor_cmd_exec(sp, MTK_NOR_CMD_READ, 6 * BITS_PER_BYTE);
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if (!ret)
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buf[0] = readb(sp->base + MTK_NOR_REG_RDATA);
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return ret;
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}
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static int mtk_nor_write_buffer_enable(struct mtk_nor *sp)
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{
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int ret;
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u32 val;
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if (sp->wbuf_en)
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return 0;
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val = readl(sp->base + MTK_NOR_REG_CFG2);
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writel(val | MTK_NOR_WR_BUF_EN, sp->base + MTK_NOR_REG_CFG2);
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ret = readl_poll_timeout(sp->base + MTK_NOR_REG_CFG2, val,
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val & MTK_NOR_WR_BUF_EN, 0, 10000);
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if (!ret)
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sp->wbuf_en = true;
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return ret;
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}
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static int mtk_nor_write_buffer_disable(struct mtk_nor *sp)
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{
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int ret;
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u32 val;
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if (!sp->wbuf_en)
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return 0;
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val = readl(sp->base + MTK_NOR_REG_CFG2);
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writel(val & ~MTK_NOR_WR_BUF_EN, sp->base + MTK_NOR_REG_CFG2);
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ret = readl_poll_timeout(sp->base + MTK_NOR_REG_CFG2, val,
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!(val & MTK_NOR_WR_BUF_EN), 0, 10000);
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if (!ret)
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sp->wbuf_en = false;
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return ret;
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}
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static int mtk_nor_pp_buffered(struct mtk_nor *sp, const struct spi_mem_op *op)
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{
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const u8 *buf = op->data.buf.out;
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u32 val;
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int ret, i;
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ret = mtk_nor_write_buffer_enable(sp);
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if (ret < 0)
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return ret;
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for (i = 0; i < op->data.nbytes; i += 4) {
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val = buf[i + 3] << 24 | buf[i + 2] << 16 | buf[i + 1] << 8 |
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buf[i];
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writel(val, sp->base + MTK_NOR_REG_PP_DATA);
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}
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return mtk_nor_cmd_exec(sp, MTK_NOR_CMD_WRITE,
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(op->data.nbytes + 5) * BITS_PER_BYTE);
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}
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static int mtk_nor_pp_unbuffered(struct mtk_nor *sp,
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const struct spi_mem_op *op)
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{
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const u8 *buf = op->data.buf.out;
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int ret;
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ret = mtk_nor_write_buffer_disable(sp);
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if (ret < 0)
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return ret;
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writeb(buf[0], sp->base + MTK_NOR_REG_WDATA);
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return mtk_nor_cmd_exec(sp, MTK_NOR_CMD_WRITE, 6 * BITS_PER_BYTE);
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}
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static int mtk_nor_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
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{
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struct mtk_nor *sp = spi_controller_get_devdata(mem->spi->master);
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int ret;
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if ((op->data.nbytes == 0) ||
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((op->addr.nbytes != 3) && (op->addr.nbytes != 4)))
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return -ENOTSUPP;
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if (op->data.dir == SPI_MEM_DATA_OUT) {
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mtk_nor_set_addr(sp, op);
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writeb(op->cmd.opcode, sp->base + MTK_NOR_REG_PRGDATA0);
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if (op->data.nbytes == MTK_NOR_PP_SIZE)
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return mtk_nor_pp_buffered(sp, op);
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return mtk_nor_pp_unbuffered(sp, op);
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}
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if ((op->data.dir == SPI_MEM_DATA_IN) && mtk_nor_match_read(op)) {
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ret = mtk_nor_write_buffer_disable(sp);
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if (ret < 0)
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return ret;
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mtk_nor_setup_bus(sp, op);
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if (op->data.nbytes == 1) {
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mtk_nor_set_addr(sp, op);
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return mtk_nor_read_pio(sp, op);
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} else if (((ulong)(op->data.buf.in) &
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MTK_NOR_DMA_ALIGN_MASK)) {
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return mtk_nor_read_bounce(sp, op->addr.val,
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op->data.nbytes,
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op->data.buf.in);
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} else {
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return mtk_nor_read_dma(sp, op->addr.val,
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op->data.nbytes,
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op->data.buf.in);
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}
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}
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return -ENOTSUPP;
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}
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static int mtk_nor_setup(struct spi_device *spi)
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{
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struct mtk_nor *sp = spi_controller_get_devdata(spi->master);
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if (spi->max_speed_hz && (spi->max_speed_hz < sp->spi_freq)) {
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dev_err(&spi->dev, "spi clock should be %u Hz.\n",
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sp->spi_freq);
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return -EINVAL;
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}
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spi->max_speed_hz = sp->spi_freq;
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return 0;
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}
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static int mtk_nor_transfer_one_message(struct spi_controller *master,
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struct spi_message *m)
|
|
{
|
|
struct mtk_nor *sp = spi_controller_get_devdata(master);
|
|
struct spi_transfer *t = NULL;
|
|
unsigned long trx_len = 0;
|
|
int stat = 0;
|
|
int reg_offset = MTK_NOR_REG_PRGDATA_MAX;
|
|
void __iomem *reg;
|
|
const u8 *txbuf;
|
|
u8 *rxbuf;
|
|
int i;
|
|
|
|
list_for_each_entry(t, &m->transfers, transfer_list) {
|
|
txbuf = t->tx_buf;
|
|
for (i = 0; i < t->len; i++, reg_offset--) {
|
|
reg = sp->base + MTK_NOR_REG_PRGDATA(reg_offset);
|
|
if (txbuf)
|
|
writeb(txbuf[i], reg);
|
|
else
|
|
writeb(0, reg);
|
|
}
|
|
trx_len += t->len;
|
|
}
|
|
|
|
writel(trx_len * BITS_PER_BYTE, sp->base + MTK_NOR_REG_PRG_CNT);
|
|
|
|
stat = mtk_nor_cmd_exec(sp, MTK_NOR_CMD_PROGRAM,
|
|
trx_len * BITS_PER_BYTE);
|
|
if (stat < 0)
|
|
goto msg_done;
|
|
|
|
reg_offset = trx_len - 1;
|
|
list_for_each_entry(t, &m->transfers, transfer_list) {
|
|
rxbuf = t->rx_buf;
|
|
for (i = 0; i < t->len; i++, reg_offset--) {
|
|
reg = sp->base + MTK_NOR_REG_SHIFT(reg_offset);
|
|
if (rxbuf)
|
|
rxbuf[i] = readb(reg);
|
|
}
|
|
}
|
|
|
|
m->actual_length = trx_len;
|
|
msg_done:
|
|
m->status = stat;
|
|
spi_finalize_current_message(master);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void mtk_nor_disable_clk(struct mtk_nor *sp)
|
|
{
|
|
clk_disable_unprepare(sp->spi_clk);
|
|
clk_disable_unprepare(sp->ctlr_clk);
|
|
}
|
|
|
|
static int mtk_nor_enable_clk(struct mtk_nor *sp)
|
|
{
|
|
int ret;
|
|
|
|
ret = clk_prepare_enable(sp->spi_clk);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = clk_prepare_enable(sp->ctlr_clk);
|
|
if (ret) {
|
|
clk_disable_unprepare(sp->spi_clk);
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int mtk_nor_init(struct mtk_nor *sp)
|
|
{
|
|
int ret;
|
|
|
|
ret = mtk_nor_enable_clk(sp);
|
|
if (ret)
|
|
return ret;
|
|
|
|
sp->spi_freq = clk_get_rate(sp->spi_clk);
|
|
|
|
writel(MTK_NOR_ENABLE_SF_CMD, sp->base + MTK_NOR_REG_WP);
|
|
mtk_nor_rmw(sp, MTK_NOR_REG_CFG2, MTK_NOR_WR_CUSTOM_OP_EN, 0);
|
|
mtk_nor_rmw(sp, MTK_NOR_REG_CFG3,
|
|
MTK_NOR_DISABLE_WREN | MTK_NOR_DISABLE_SR_POLL, 0);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static irqreturn_t mtk_nor_irq_handler(int irq, void *data)
|
|
{
|
|
struct mtk_nor *sp = data;
|
|
u32 irq_status, irq_enabled;
|
|
|
|
irq_status = readl(sp->base + MTK_NOR_REG_IRQ_STAT);
|
|
irq_enabled = readl(sp->base + MTK_NOR_REG_IRQ_EN);
|
|
// write status back to clear interrupt
|
|
writel(irq_status, sp->base + MTK_NOR_REG_IRQ_STAT);
|
|
|
|
if (!(irq_status & irq_enabled))
|
|
return IRQ_NONE;
|
|
|
|
if (irq_status & MTK_NOR_IRQ_DMA) {
|
|
complete(&sp->op_done);
|
|
writel(0, sp->base + MTK_NOR_REG_IRQ_EN);
|
|
}
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static size_t mtk_max_msg_size(struct spi_device *spi)
|
|
{
|
|
return MTK_NOR_PRG_MAX_SIZE;
|
|
}
|
|
|
|
static const struct spi_controller_mem_ops mtk_nor_mem_ops = {
|
|
.adjust_op_size = mtk_nor_adjust_op_size,
|
|
.supports_op = mtk_nor_supports_op,
|
|
.exec_op = mtk_nor_exec_op
|
|
};
|
|
|
|
static const struct of_device_id mtk_nor_match[] = {
|
|
{ .compatible = "mediatek,mt8173-nor" },
|
|
{ /* sentinel */ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, mtk_nor_match);
|
|
|
|
static int mtk_nor_probe(struct platform_device *pdev)
|
|
{
|
|
struct spi_controller *ctlr;
|
|
struct mtk_nor *sp;
|
|
void __iomem *base;
|
|
u8 *buffer;
|
|
struct clk *spi_clk, *ctlr_clk;
|
|
int ret, irq;
|
|
|
|
base = devm_platform_ioremap_resource(pdev, 0);
|
|
if (IS_ERR(base))
|
|
return PTR_ERR(base);
|
|
|
|
spi_clk = devm_clk_get(&pdev->dev, "spi");
|
|
if (IS_ERR(spi_clk))
|
|
return PTR_ERR(spi_clk);
|
|
|
|
ctlr_clk = devm_clk_get(&pdev->dev, "sf");
|
|
if (IS_ERR(ctlr_clk))
|
|
return PTR_ERR(ctlr_clk);
|
|
|
|
buffer = devm_kmalloc(&pdev->dev,
|
|
MTK_NOR_BOUNCE_BUF_SIZE + MTK_NOR_DMA_ALIGN,
|
|
GFP_KERNEL);
|
|
if (!buffer)
|
|
return -ENOMEM;
|
|
|
|
if ((ulong)buffer & MTK_NOR_DMA_ALIGN_MASK)
|
|
buffer = (u8 *)(((ulong)buffer + MTK_NOR_DMA_ALIGN) &
|
|
~MTK_NOR_DMA_ALIGN_MASK);
|
|
|
|
ctlr = spi_alloc_master(&pdev->dev, sizeof(*sp));
|
|
if (!ctlr) {
|
|
dev_err(&pdev->dev, "failed to allocate spi controller\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
|
|
ctlr->dev.of_node = pdev->dev.of_node;
|
|
ctlr->max_message_size = mtk_max_msg_size;
|
|
ctlr->mem_ops = &mtk_nor_mem_ops;
|
|
ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | SPI_TX_DUAL | SPI_TX_QUAD;
|
|
ctlr->num_chipselect = 1;
|
|
ctlr->setup = mtk_nor_setup;
|
|
ctlr->transfer_one_message = mtk_nor_transfer_one_message;
|
|
|
|
dev_set_drvdata(&pdev->dev, ctlr);
|
|
|
|
sp = spi_controller_get_devdata(ctlr);
|
|
sp->base = base;
|
|
sp->buffer = buffer;
|
|
sp->has_irq = false;
|
|
sp->wbuf_en = false;
|
|
sp->ctlr = ctlr;
|
|
sp->dev = &pdev->dev;
|
|
sp->spi_clk = spi_clk;
|
|
sp->ctlr_clk = ctlr_clk;
|
|
|
|
irq = platform_get_irq_optional(pdev, 0);
|
|
if (irq < 0) {
|
|
dev_warn(sp->dev, "IRQ not available.");
|
|
} else {
|
|
writel(MTK_NOR_IRQ_MASK, base + MTK_NOR_REG_IRQ_STAT);
|
|
writel(0, base + MTK_NOR_REG_IRQ_EN);
|
|
ret = devm_request_irq(sp->dev, irq, mtk_nor_irq_handler, 0,
|
|
pdev->name, sp);
|
|
if (ret < 0) {
|
|
dev_warn(sp->dev, "failed to request IRQ.");
|
|
} else {
|
|
init_completion(&sp->op_done);
|
|
sp->has_irq = true;
|
|
}
|
|
}
|
|
|
|
ret = mtk_nor_init(sp);
|
|
if (ret < 0) {
|
|
kfree(ctlr);
|
|
return ret;
|
|
}
|
|
|
|
dev_info(&pdev->dev, "spi frequency: %d Hz\n", sp->spi_freq);
|
|
|
|
return devm_spi_register_controller(&pdev->dev, ctlr);
|
|
}
|
|
|
|
static int mtk_nor_remove(struct platform_device *pdev)
|
|
{
|
|
struct spi_controller *ctlr;
|
|
struct mtk_nor *sp;
|
|
|
|
ctlr = dev_get_drvdata(&pdev->dev);
|
|
sp = spi_controller_get_devdata(ctlr);
|
|
|
|
mtk_nor_disable_clk(sp);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver mtk_nor_driver = {
|
|
.driver = {
|
|
.name = DRIVER_NAME,
|
|
.of_match_table = mtk_nor_match,
|
|
},
|
|
.probe = mtk_nor_probe,
|
|
.remove = mtk_nor_remove,
|
|
};
|
|
|
|
module_platform_driver(mtk_nor_driver);
|
|
|
|
MODULE_DESCRIPTION("Mediatek SPI NOR controller driver");
|
|
MODULE_AUTHOR("Chuanhong Guo <gch981213@gmail.com>");
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_ALIAS("platform:" DRIVER_NAME);
|