mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-27 02:55:42 +07:00
0b84933db7
The G12A Primary plane was disabled by writing in the OSD1 configuration
registers, but this caused the plane blender to stall instead of continuing
to blend only the overlay plane.
Fix this by disabling the OSD1 plane in the blender registers, and also
enabling it back using the same register.
Fixes: 490f50c109 ("drm/meson: Add G12A support for OSD1 Plane")
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
[narmstrong: fixed nit in commit log]
Link: https://patchwork.freedesktop.org/patch/msgid/20190605141253.24165-3-narmstrong@baylibre.com
426 lines
13 KiB
C
426 lines
13 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) 2016 BayLibre, SAS
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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* Copyright (C) 2015 Amlogic, Inc. All rights reserved.
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* Copyright (C) 2014 Endless Mobile
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <drm/drmP.h>
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#include "meson_drv.h"
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#include "meson_viu.h"
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#include "meson_vpp.h"
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#include "meson_venc.h"
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#include "meson_registers.h"
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/**
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* DOC: Video Input Unit
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*
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* VIU Handles the Pixel scanout and the basic Colorspace conversions
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* We handle the following features :
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*
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* - OSD1 RGB565/RGB888/xRGB8888 scanout
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* - RGB conversion to x/cb/cr
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* - Progressive or Interlace buffer scanout
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* - OSD1 Commit on Vsync
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* - HDR OSD matrix for GXL/GXM
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*
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* What is missing :
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*
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* - BGR888/xBGR8888/BGRx8888/BGRx8888 modes
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* - YUV4:2:2 Y0CbY1Cr scanout
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* - Conversion to YUV 4:4:4 from 4:2:2 input
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* - Colorkey Alpha matching
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* - Big endian scanout
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* - X/Y reverse scanout
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* - Global alpha setup
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* - OSD2 support, would need interlace switching on vsync
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* - OSD1 full scaling to support TV overscan
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*/
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/* OSD csc defines */
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enum viu_matrix_sel_e {
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VIU_MATRIX_OSD_EOTF = 0,
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VIU_MATRIX_OSD,
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};
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enum viu_lut_sel_e {
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VIU_LUT_OSD_EOTF = 0,
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VIU_LUT_OSD_OETF,
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};
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#define COEFF_NORM(a) ((int)((((a) * 2048.0) + 1) / 2))
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#define MATRIX_5X3_COEF_SIZE 24
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#define EOTF_COEFF_NORM(a) ((int)((((a) * 4096.0) + 1) / 2))
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#define EOTF_COEFF_SIZE 10
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#define EOTF_COEFF_RIGHTSHIFT 1
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static int RGB709_to_YUV709l_coeff[MATRIX_5X3_COEF_SIZE] = {
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0, 0, 0, /* pre offset */
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COEFF_NORM(0.181873), COEFF_NORM(0.611831), COEFF_NORM(0.061765),
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COEFF_NORM(-0.100251), COEFF_NORM(-0.337249), COEFF_NORM(0.437500),
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COEFF_NORM(0.437500), COEFF_NORM(-0.397384), COEFF_NORM(-0.040116),
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0, 0, 0, /* 10'/11'/12' */
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0, 0, 0, /* 20'/21'/22' */
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64, 512, 512, /* offset */
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0, 0, 0 /* mode, right_shift, clip_en */
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};
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/* eotf matrix: bypass */
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static int eotf_bypass_coeff[EOTF_COEFF_SIZE] = {
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EOTF_COEFF_NORM(1.0), EOTF_COEFF_NORM(0.0), EOTF_COEFF_NORM(0.0),
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EOTF_COEFF_NORM(0.0), EOTF_COEFF_NORM(1.0), EOTF_COEFF_NORM(0.0),
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EOTF_COEFF_NORM(0.0), EOTF_COEFF_NORM(0.0), EOTF_COEFF_NORM(1.0),
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EOTF_COEFF_RIGHTSHIFT /* right shift */
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};
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static void meson_viu_set_g12a_osd1_matrix(struct meson_drm *priv,
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int *m, bool csc_on)
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{
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/* VPP WRAP OSD1 matrix */
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writel(((m[0] & 0xfff) << 16) | (m[1] & 0xfff),
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priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_PRE_OFFSET0_1));
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writel(m[2] & 0xfff,
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priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_PRE_OFFSET2));
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writel(((m[3] & 0x1fff) << 16) | (m[4] & 0x1fff),
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priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF00_01));
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writel(((m[5] & 0x1fff) << 16) | (m[6] & 0x1fff),
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priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF02_10));
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writel(((m[7] & 0x1fff) << 16) | (m[8] & 0x1fff),
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priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF11_12));
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writel(((m[9] & 0x1fff) << 16) | (m[10] & 0x1fff),
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priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF20_21));
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writel((m[11] & 0x1fff) << 16,
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priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF22));
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writel(((m[18] & 0xfff) << 16) | (m[19] & 0xfff),
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priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_OFFSET0_1));
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writel(m[20] & 0xfff,
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priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_OFFSET2));
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writel_bits_relaxed(BIT(0), csc_on ? BIT(0) : 0,
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priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_EN_CTRL));
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}
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static void meson_viu_set_osd_matrix(struct meson_drm *priv,
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enum viu_matrix_sel_e m_select,
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int *m, bool csc_on)
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{
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if (m_select == VIU_MATRIX_OSD) {
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/* osd matrix, VIU_MATRIX_0 */
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writel(((m[0] & 0xfff) << 16) | (m[1] & 0xfff),
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priv->io_base + _REG(VIU_OSD1_MATRIX_PRE_OFFSET0_1));
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writel(m[2] & 0xfff,
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priv->io_base + _REG(VIU_OSD1_MATRIX_PRE_OFFSET2));
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writel(((m[3] & 0x1fff) << 16) | (m[4] & 0x1fff),
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priv->io_base + _REG(VIU_OSD1_MATRIX_COEF00_01));
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writel(((m[5] & 0x1fff) << 16) | (m[6] & 0x1fff),
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priv->io_base + _REG(VIU_OSD1_MATRIX_COEF02_10));
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writel(((m[7] & 0x1fff) << 16) | (m[8] & 0x1fff),
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priv->io_base + _REG(VIU_OSD1_MATRIX_COEF11_12));
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writel(((m[9] & 0x1fff) << 16) | (m[10] & 0x1fff),
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priv->io_base + _REG(VIU_OSD1_MATRIX_COEF20_21));
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if (m[21]) {
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writel(((m[11] & 0x1fff) << 16) | (m[12] & 0x1fff),
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priv->io_base +
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_REG(VIU_OSD1_MATRIX_COEF22_30));
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writel(((m[13] & 0x1fff) << 16) | (m[14] & 0x1fff),
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priv->io_base +
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_REG(VIU_OSD1_MATRIX_COEF31_32));
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writel(((m[15] & 0x1fff) << 16) | (m[16] & 0x1fff),
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priv->io_base +
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_REG(VIU_OSD1_MATRIX_COEF40_41));
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writel(m[17] & 0x1fff, priv->io_base +
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_REG(VIU_OSD1_MATRIX_COLMOD_COEF42));
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} else
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writel((m[11] & 0x1fff) << 16, priv->io_base +
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_REG(VIU_OSD1_MATRIX_COEF22_30));
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writel(((m[18] & 0xfff) << 16) | (m[19] & 0xfff),
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priv->io_base + _REG(VIU_OSD1_MATRIX_OFFSET0_1));
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writel(m[20] & 0xfff,
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priv->io_base + _REG(VIU_OSD1_MATRIX_OFFSET2));
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writel_bits_relaxed(3 << 30, m[21] << 30,
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priv->io_base + _REG(VIU_OSD1_MATRIX_COLMOD_COEF42));
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writel_bits_relaxed(7 << 16, m[22] << 16,
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priv->io_base + _REG(VIU_OSD1_MATRIX_COLMOD_COEF42));
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/* 23 reserved for clipping control */
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writel_bits_relaxed(BIT(0), csc_on ? BIT(0) : 0,
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priv->io_base + _REG(VIU_OSD1_MATRIX_CTRL));
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writel_bits_relaxed(BIT(1), 0,
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priv->io_base + _REG(VIU_OSD1_MATRIX_CTRL));
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} else if (m_select == VIU_MATRIX_OSD_EOTF) {
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int i;
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/* osd eotf matrix, VIU_MATRIX_OSD_EOTF */
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for (i = 0; i < 5; i++)
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writel(((m[i * 2] & 0x1fff) << 16) |
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(m[i * 2 + 1] & 0x1fff), priv->io_base +
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_REG(VIU_OSD1_EOTF_CTL + i + 1));
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writel_bits_relaxed(BIT(30), csc_on ? BIT(30) : 0,
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priv->io_base + _REG(VIU_OSD1_EOTF_CTL));
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writel_bits_relaxed(BIT(31), csc_on ? BIT(31) : 0,
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priv->io_base + _REG(VIU_OSD1_EOTF_CTL));
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}
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}
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#define OSD_EOTF_LUT_SIZE 33
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#define OSD_OETF_LUT_SIZE 41
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static void
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meson_viu_set_osd_lut(struct meson_drm *priv, enum viu_lut_sel_e lut_sel,
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unsigned int *r_map, unsigned int *g_map,
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unsigned int *b_map, bool csc_on)
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{
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unsigned int addr_port;
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unsigned int data_port;
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unsigned int ctrl_port;
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int i;
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if (lut_sel == VIU_LUT_OSD_EOTF) {
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addr_port = VIU_OSD1_EOTF_LUT_ADDR_PORT;
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data_port = VIU_OSD1_EOTF_LUT_DATA_PORT;
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ctrl_port = VIU_OSD1_EOTF_CTL;
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} else if (lut_sel == VIU_LUT_OSD_OETF) {
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addr_port = VIU_OSD1_OETF_LUT_ADDR_PORT;
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data_port = VIU_OSD1_OETF_LUT_DATA_PORT;
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ctrl_port = VIU_OSD1_OETF_CTL;
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} else
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return;
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if (lut_sel == VIU_LUT_OSD_OETF) {
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writel(0, priv->io_base + _REG(addr_port));
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for (i = 0; i < (OSD_OETF_LUT_SIZE / 2); i++)
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writel(r_map[i * 2] | (r_map[i * 2 + 1] << 16),
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priv->io_base + _REG(data_port));
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writel(r_map[OSD_OETF_LUT_SIZE - 1] | (g_map[0] << 16),
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priv->io_base + _REG(data_port));
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for (i = 0; i < (OSD_OETF_LUT_SIZE / 2); i++)
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writel(g_map[i * 2 + 1] | (g_map[i * 2 + 2] << 16),
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priv->io_base + _REG(data_port));
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for (i = 0; i < (OSD_OETF_LUT_SIZE / 2); i++)
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writel(b_map[i * 2] | (b_map[i * 2 + 1] << 16),
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priv->io_base + _REG(data_port));
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writel(b_map[OSD_OETF_LUT_SIZE - 1],
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priv->io_base + _REG(data_port));
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if (csc_on)
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writel_bits_relaxed(0x7 << 29, 7 << 29,
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priv->io_base + _REG(ctrl_port));
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else
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writel_bits_relaxed(0x7 << 29, 0,
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priv->io_base + _REG(ctrl_port));
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} else if (lut_sel == VIU_LUT_OSD_EOTF) {
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writel(0, priv->io_base + _REG(addr_port));
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for (i = 0; i < (OSD_EOTF_LUT_SIZE / 2); i++)
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writel(r_map[i * 2] | (r_map[i * 2 + 1] << 16),
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priv->io_base + _REG(data_port));
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writel(r_map[OSD_EOTF_LUT_SIZE - 1] | (g_map[0] << 16),
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priv->io_base + _REG(data_port));
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for (i = 0; i < (OSD_EOTF_LUT_SIZE / 2); i++)
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writel(g_map[i * 2 + 1] | (g_map[i * 2 + 2] << 16),
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priv->io_base + _REG(data_port));
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for (i = 0; i < (OSD_EOTF_LUT_SIZE / 2); i++)
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writel(b_map[i * 2] | (b_map[i * 2 + 1] << 16),
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priv->io_base + _REG(data_port));
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writel(b_map[OSD_EOTF_LUT_SIZE - 1],
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priv->io_base + _REG(data_port));
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if (csc_on)
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writel_bits_relaxed(7 << 27, 7 << 27,
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priv->io_base + _REG(ctrl_port));
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else
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writel_bits_relaxed(7 << 27, 0,
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priv->io_base + _REG(ctrl_port));
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writel_bits_relaxed(BIT(31), BIT(31),
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priv->io_base + _REG(ctrl_port));
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}
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}
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/* eotf lut: linear */
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static unsigned int eotf_33_linear_mapping[OSD_EOTF_LUT_SIZE] = {
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0x0000, 0x0200, 0x0400, 0x0600,
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0x0800, 0x0a00, 0x0c00, 0x0e00,
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0x1000, 0x1200, 0x1400, 0x1600,
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0x1800, 0x1a00, 0x1c00, 0x1e00,
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0x2000, 0x2200, 0x2400, 0x2600,
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0x2800, 0x2a00, 0x2c00, 0x2e00,
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0x3000, 0x3200, 0x3400, 0x3600,
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0x3800, 0x3a00, 0x3c00, 0x3e00,
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0x4000
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};
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/* osd oetf lut: linear */
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static unsigned int oetf_41_linear_mapping[OSD_OETF_LUT_SIZE] = {
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0, 0, 0, 0,
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0, 32, 64, 96,
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128, 160, 196, 224,
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256, 288, 320, 352,
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384, 416, 448, 480,
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512, 544, 576, 608,
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640, 672, 704, 736,
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768, 800, 832, 864,
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896, 928, 960, 992,
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1023, 1023, 1023, 1023,
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1023
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};
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static void meson_viu_load_matrix(struct meson_drm *priv)
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{
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/* eotf lut bypass */
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meson_viu_set_osd_lut(priv, VIU_LUT_OSD_EOTF,
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eotf_33_linear_mapping, /* R */
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eotf_33_linear_mapping, /* G */
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eotf_33_linear_mapping, /* B */
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false);
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/* eotf matrix bypass */
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meson_viu_set_osd_matrix(priv, VIU_MATRIX_OSD_EOTF,
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eotf_bypass_coeff,
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false);
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/* oetf lut bypass */
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meson_viu_set_osd_lut(priv, VIU_LUT_OSD_OETF,
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oetf_41_linear_mapping, /* R */
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oetf_41_linear_mapping, /* G */
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oetf_41_linear_mapping, /* B */
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false);
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/* osd matrix RGB709 to YUV709 limit */
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meson_viu_set_osd_matrix(priv, VIU_MATRIX_OSD,
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RGB709_to_YUV709l_coeff,
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true);
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}
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/* VIU OSD1 Reset as workaround for GXL+ Alpha OSD Bug */
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void meson_viu_osd1_reset(struct meson_drm *priv)
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{
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uint32_t osd1_fifo_ctrl_stat, osd1_ctrl_stat2;
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/* Save these 2 registers state */
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osd1_fifo_ctrl_stat = readl_relaxed(
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priv->io_base + _REG(VIU_OSD1_FIFO_CTRL_STAT));
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osd1_ctrl_stat2 = readl_relaxed(
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priv->io_base + _REG(VIU_OSD1_CTRL_STAT2));
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/* Reset OSD1 */
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writel_bits_relaxed(BIT(0), BIT(0),
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priv->io_base + _REG(VIU_SW_RESET));
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writel_bits_relaxed(BIT(0), 0,
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priv->io_base + _REG(VIU_SW_RESET));
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/* Rewrite these registers state lost in the reset */
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writel_relaxed(osd1_fifo_ctrl_stat,
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priv->io_base + _REG(VIU_OSD1_FIFO_CTRL_STAT));
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writel_relaxed(osd1_ctrl_stat2,
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priv->io_base + _REG(VIU_OSD1_CTRL_STAT2));
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/* Reload the conversion matrix */
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meson_viu_load_matrix(priv);
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}
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void meson_viu_init(struct meson_drm *priv)
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{
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uint32_t reg;
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/* Disable OSDs */
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writel_bits_relaxed(BIT(0) | BIT(21), 0,
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priv->io_base + _REG(VIU_OSD1_CTRL_STAT));
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writel_bits_relaxed(BIT(0) | BIT(21), 0,
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priv->io_base + _REG(VIU_OSD2_CTRL_STAT));
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/* On GXL/GXM, Use the 10bit HDR conversion matrix */
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if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu") ||
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meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu"))
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meson_viu_load_matrix(priv);
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else if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu"))
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meson_viu_set_g12a_osd1_matrix(priv, RGB709_to_YUV709l_coeff,
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true);
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/* Initialize OSD1 fifo control register */
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reg = BIT(0) | /* Urgent DDR request priority */
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(4 << 5); /* hold_fifo_lines */
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if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu"))
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reg |= (1 << 10) | /* burst length 32 */
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(32 << 12) | /* fifo_depth_val: 32*8=256 */
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(2 << 22) | /* 4 words in 1 burst */
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(2 << 24) |
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(1 << 31);
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else
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reg |= (3 << 10) | /* burst length 64 */
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(32 << 12) | /* fifo_depth_val: 32*8=256 */
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(2 << 22) | /* 4 words in 1 burst */
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(2 << 24);
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writel_relaxed(reg, priv->io_base + _REG(VIU_OSD1_FIFO_CTRL_STAT));
|
|
writel_relaxed(reg, priv->io_base + _REG(VIU_OSD2_FIFO_CTRL_STAT));
|
|
|
|
/* Set OSD alpha replace value */
|
|
writel_bits_relaxed(0xff << OSD_REPLACE_SHIFT,
|
|
0xff << OSD_REPLACE_SHIFT,
|
|
priv->io_base + _REG(VIU_OSD1_CTRL_STAT2));
|
|
writel_bits_relaxed(0xff << OSD_REPLACE_SHIFT,
|
|
0xff << OSD_REPLACE_SHIFT,
|
|
priv->io_base + _REG(VIU_OSD2_CTRL_STAT2));
|
|
|
|
/* Disable VD1 AFBC */
|
|
/* di_mif0_en=0 mif0_to_vpp_en=0 di_mad_en=0 */
|
|
writel_bits_relaxed(0x7 << 16, 0,
|
|
priv->io_base + _REG(VIU_MISC_CTRL0));
|
|
/* afbc vd1 set=0 */
|
|
writel_bits_relaxed(BIT(20), 0,
|
|
priv->io_base + _REG(VIU_MISC_CTRL0));
|
|
writel_relaxed(0, priv->io_base + _REG(AFBC_ENABLE));
|
|
|
|
writel_relaxed(0x00FF00C0,
|
|
priv->io_base + _REG(VD1_IF0_LUMA_FIFO_SIZE));
|
|
writel_relaxed(0x00FF00C0,
|
|
priv->io_base + _REG(VD2_IF0_LUMA_FIFO_SIZE));
|
|
|
|
if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu")) {
|
|
writel_relaxed(4 << 29 |
|
|
1 << 27 |
|
|
1 << 26 | /* blend_din0 input to blend0 */
|
|
1 << 25 | /* blend1_dout to blend2 */
|
|
1 << 24 | /* blend1_din3 input to blend1 */
|
|
1 << 20 |
|
|
0 << 16 |
|
|
1,
|
|
priv->io_base + _REG(VIU_OSD_BLEND_CTRL));
|
|
writel_relaxed(1 << 20,
|
|
priv->io_base + _REG(OSD1_BLEND_SRC_CTRL));
|
|
writel_relaxed(1 << 20,
|
|
priv->io_base + _REG(OSD2_BLEND_SRC_CTRL));
|
|
writel_relaxed(0, priv->io_base + _REG(VD1_BLEND_SRC_CTRL));
|
|
writel_relaxed(0, priv->io_base + _REG(VD2_BLEND_SRC_CTRL));
|
|
writel_relaxed(0,
|
|
priv->io_base + _REG(VIU_OSD_BLEND_DUMMY_DATA0));
|
|
writel_relaxed(0,
|
|
priv->io_base + _REG(VIU_OSD_BLEND_DUMMY_ALPHA));
|
|
writel_bits_relaxed(0x3 << 2, 0x3 << 2,
|
|
priv->io_base + _REG(DOLBY_PATH_CTRL));
|
|
}
|
|
|
|
priv->viu.osd1_enabled = false;
|
|
priv->viu.osd1_commit = false;
|
|
priv->viu.osd1_interlace = false;
|
|
}
|