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a1ce39288e
Convert #include "..." to #include <path/...> in kernel system headers. Signed-off-by: David Howells <dhowells@redhat.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com> Acked-by: Dave Jones <davej@redhat.com>
140 lines
5.1 KiB
C
140 lines
5.1 KiB
C
/***********************license start***************
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* Author: Cavium Networks
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*
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* Contact: support@caviumnetworks.com
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* This file is part of the OCTEON SDK
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*
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* Copyright (c) 2003-2008 Cavium Networks
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*
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* This file is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, Version 2, as
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* published by the Free Software Foundation.
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*
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* This file is distributed in the hope that it will be useful, but
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* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
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* NONINFRINGEMENT. See the GNU General Public License for more
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* details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this file; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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* or visit http://www.gnu.org/licenses/.
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*
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* This file may also be available under a different license from Cavium.
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* Contact Cavium Networks for more information
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***********************license end**************************************/
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/*
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*
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* This is file defines ASM primitives for the executive.
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*/
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#ifndef __CVMX_ASM_H__
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#define __CVMX_ASM_H__
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#include <asm/octeon/octeon-model.h>
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/* other useful stuff */
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#define CVMX_SYNC asm volatile ("sync" : : : "memory")
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/* String version of SYNCW macro for using in inline asm constructs */
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#define CVMX_SYNCW_STR "syncw\nsyncw\n"
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#ifdef __OCTEON__
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/* Deprecated, will be removed in future release */
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#define CVMX_SYNCIO asm volatile ("nop")
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#define CVMX_SYNCIOBDMA asm volatile ("synciobdma" : : : "memory")
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/* Deprecated, will be removed in future release */
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#define CVMX_SYNCIOALL asm volatile ("nop")
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/*
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* We actually use two syncw instructions in a row when we need a write
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* memory barrier. This is because the CN3XXX series of Octeons have
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* errata Core-401. This can cause a single syncw to not enforce
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* ordering under very rare conditions. Even if it is rare, better safe
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* than sorry.
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*/
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#define CVMX_SYNCW asm volatile ("syncw\n\tsyncw" : : : "memory")
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/*
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* Define new sync instructions to be normal SYNC instructions for
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* operating systems that use threads.
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*/
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#define CVMX_SYNCWS CVMX_SYNCW
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#define CVMX_SYNCS CVMX_SYNC
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#define CVMX_SYNCWS_STR CVMX_SYNCW_STR
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#else
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/*
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* Not using a Cavium compiler, always use the slower sync so the
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* assembler stays happy.
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*/
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/* Deprecated, will be removed in future release */
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#define CVMX_SYNCIO asm volatile ("nop")
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#define CVMX_SYNCIOBDMA asm volatile ("sync" : : : "memory")
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/* Deprecated, will be removed in future release */
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#define CVMX_SYNCIOALL asm volatile ("nop")
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#define CVMX_SYNCW asm volatile ("sync" : : : "memory")
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#define CVMX_SYNCWS CVMX_SYNCW
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#define CVMX_SYNCS CVMX_SYNC
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#define CVMX_SYNCWS_STR CVMX_SYNCW_STR
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#endif
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/*
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* CVMX_PREPARE_FOR_STORE makes each byte of the block unpredictable
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* (actually old value or zero) until that byte is stored to (by this or
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* another processor. Note that the value of each byte is not only
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* unpredictable, but may also change again - up until the point when one
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* of the cores stores to the byte.
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*/
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#define CVMX_PREPARE_FOR_STORE(address, offset) \
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asm volatile ("pref 30, " CVMX_TMP_STR(offset) "(%[rbase])" : : \
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[rbase] "d" (address))
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/*
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* This is a command headed to the L2 controller to tell it to clear
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* its dirty bit for a block. Basically, SW is telling HW that the
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* current version of the block will not be used.
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*/
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#define CVMX_DONT_WRITE_BACK(address, offset) \
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asm volatile ("pref 29, " CVMX_TMP_STR(offset) "(%[rbase])" : : \
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[rbase] "d" (address))
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/* flush stores, invalidate entire icache */
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#define CVMX_ICACHE_INVALIDATE \
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{ CVMX_SYNC; asm volatile ("synci 0($0)" : : ); }
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/* flush stores, invalidate entire icache */
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#define CVMX_ICACHE_INVALIDATE2 \
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{ CVMX_SYNC; asm volatile ("cache 0, 0($0)" : : ); }
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/* complete prefetches, invalidate entire dcache */
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#define CVMX_DCACHE_INVALIDATE \
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{ CVMX_SYNC; asm volatile ("cache 9, 0($0)" : : ); }
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#define CVMX_CACHE(op, address, offset) \
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asm volatile ("cache " CVMX_TMP_STR(op) ", " CVMX_TMP_STR(offset) "(%[rbase])" \
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: : [rbase] "d" (address) )
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/* fetch and lock the state. */
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#define CVMX_CACHE_LCKL2(address, offset) CVMX_CACHE(31, address, offset)
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/* unlock the state. */
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#define CVMX_CACHE_WBIL2(address, offset) CVMX_CACHE(23, address, offset)
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/* invalidate the cache block and clear the USED bits for the block */
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#define CVMX_CACHE_WBIL2I(address, offset) CVMX_CACHE(3, address, offset)
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/* load virtual tag and data for the L2 cache block into L2C_TAD0_TAG register */
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#define CVMX_CACHE_LTGL2I(address, offset) CVMX_CACHE(7, address, offset)
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#define CVMX_POP(result, input) \
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asm ("pop %[rd],%[rs]" : [rd] "=d" (result) : [rs] "d" (input))
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#define CVMX_DPOP(result, input) \
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asm ("dpop %[rd],%[rs]" : [rd] "=d" (result) : [rs] "d" (input))
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/* some new cop0-like stuff */
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#define CVMX_RDHWR(result, regstr) \
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asm volatile ("rdhwr %[rt],$" CVMX_TMP_STR(regstr) : [rt] "=d" (result))
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#define CVMX_RDHWRNV(result, regstr) \
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asm ("rdhwr %[rt],$" CVMX_TMP_STR(regstr) : [rt] "=d" (result))
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#endif /* __CVMX_ASM_H__ */
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