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CBR (core-to-bus ratio) packets provide an indication of CPU frequency. A more accurate measure can be made by counting the cycles (given by CYC packets) in between other timing packets (either MTC or TSC). Using TSC packets has at least 2 issues: 1) timing might have stopped (e.g. mwait) or 2) TSC packets within PSB+ might slip past CYC packets. For now, simply do not use TSC packets for calculating CPU cycles to TSC. That leaves the case where 2 MTC packets are used, otherwise falling back to the CBR value. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Cc: Andi Kleen <ak@linux.intel.com> Link: http://lkml.kernel.org/r/1495786658-18063-37-git-send-email-adrian.hunter@intel.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com> |
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| .. | ||
| Build | ||
| gen-insn-attr-x86.awk | ||
| inat_types.h | ||
| inat.c | ||
| inat.h | ||
| insn.c | ||
| insn.h | ||
| intel-pt-decoder.c | ||
| intel-pt-decoder.h | ||
| intel-pt-insn-decoder.c | ||
| intel-pt-insn-decoder.h | ||
| intel-pt-log.c | ||
| intel-pt-log.h | ||
| intel-pt-pkt-decoder.c | ||
| intel-pt-pkt-decoder.h | ||
| x86-opcode-map.txt | ||