mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-27 05:05:29 +07:00
e6cbf9984e
The only way for a fixed factor clock to change its rate would be to change its parent rate. Since passing blindly CLK_SET_RATE_PARENT might break a lot of platforms that were relying on the fact that the parent rate wouldn't change, introduce a compatible-based whitelist that will allow clocks to opt-in that flag. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
29 lines
733 B
Plaintext
29 lines
733 B
Plaintext
Binding for simple fixed factor rate clock sources.
|
|
|
|
This binding uses the common clock binding[1].
|
|
|
|
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
|
|
|
Required properties:
|
|
- compatible : shall be "fixed-factor-clock".
|
|
- #clock-cells : from common clock binding; shall be set to 0.
|
|
- clock-div: fixed divider.
|
|
- clock-mult: fixed multiplier.
|
|
- clocks: parent clock.
|
|
|
|
Optional properties:
|
|
- clock-output-names : From common clock binding.
|
|
|
|
Some clocks that require special treatments are also handled by that
|
|
driver, with the compatibles:
|
|
- allwinner,sun4i-a10-pll3-2x-clk
|
|
|
|
Example:
|
|
clock {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&parentclk>;
|
|
#clock-cells = <0>;
|
|
clock-div = <2>;
|
|
clock-mult = <1>;
|
|
};
|