mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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78b42c99af
Signed-off-by: Michal Piotrowski <michal.k.k.piotrowski@gmail.com> Signed-off-by: Adrian Bunk <bunk@kernel.org>
288 lines
9.5 KiB
C
288 lines
9.5 KiB
C
/*
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* icom.h
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*
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* Copyright (C) 2001 Michael Anderson, IBM Corporation
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*
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* Serial device driver include file.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/serial_core.h>
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#define BAUD_TABLE_LIMIT ((sizeof(icom_acfg_baud)/sizeof(int)) - 1)
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static int icom_acfg_baud[] = {
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300,
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600,
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900,
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1200,
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1800,
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2400,
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3600,
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4800,
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7200,
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9600,
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14400,
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19200,
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28800,
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38400,
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57600,
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76800,
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115200,
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153600,
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230400,
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307200,
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460800,
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};
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struct icom_regs {
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u32 control; /* Adapter Control Register */
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u32 interrupt; /* Adapter Interrupt Register */
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u32 int_mask; /* Adapter Interrupt Mask Reg */
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u32 int_pri; /* Adapter Interrupt Priority r */
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u32 int_reg_b; /* Adapter non-masked Interrupt */
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u32 resvd01;
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u32 resvd02;
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u32 resvd03;
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u32 control_2; /* Adapter Control Register 2 */
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u32 interrupt_2; /* Adapter Interrupt Register 2 */
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u32 int_mask_2; /* Adapter Interrupt Mask 2 */
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u32 int_pri_2; /* Adapter Interrupt Prior 2 */
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u32 int_reg_2b; /* Adapter non-masked 2 */
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};
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struct func_dram {
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u32 reserved[108]; /* 0-1B0 reserved by personality code */
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u32 RcvStatusAddr; /* 1B0-1B3 Status Address for Next rcv */
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u8 RcvStnAddr; /* 1B4 Receive Station Addr */
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u8 IdleState; /* 1B5 Idle State */
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u8 IdleMonitor; /* 1B6 Idle Monitor */
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u8 FlagFillIdleTimer; /* 1B7 Flag Fill Idle Timer */
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u32 XmitStatusAddr; /* 1B8-1BB Transmit Status Address */
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u8 StartXmitCmd; /* 1BC Start Xmit Command */
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u8 HDLCConfigReg; /* 1BD Reserved */
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u8 CauseCode; /* 1BE Cause code for fatal error */
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u8 xchar; /* 1BF High priority send */
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u32 reserved3; /* 1C0-1C3 Reserved */
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u8 PrevCmdReg; /* 1C4 Reserved */
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u8 CmdReg; /* 1C5 Command Register */
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u8 async_config2; /* 1C6 Async Config Byte 2 */
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u8 async_config3; /* 1C7 Async Config Byte 3 */
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u8 dce_resvd[20]; /* 1C8-1DB DCE Rsvd */
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u8 dce_resvd21; /* 1DC DCE Rsvd (21st byte */
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u8 misc_flags; /* 1DD misc flags */
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#define V2_HARDWARE 0x40
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#define ICOM_HDW_ACTIVE 0x01
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u8 call_length; /* 1DE Phone #/CFI buff ln */
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u8 call_length2; /* 1DF Upper byte (unused) */
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u32 call_addr; /* 1E0-1E3 Phn #/CFI buff addr */
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u16 timer_value; /* 1E4-1E5 general timer value */
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u8 timer_command; /* 1E6 general timer cmd */
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u8 dce_command; /* 1E7 dce command reg */
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u8 dce_cmd_status; /* 1E8 dce command stat */
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u8 x21_r1_ioff; /* 1E9 dce ready counter */
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u8 x21_r0_ioff; /* 1EA dce not ready ctr */
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u8 x21_ralt_ioff; /* 1EB dce CNR counter */
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u8 x21_r1_ion; /* 1EC dce ready I on ctr */
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u8 rsvd_ier; /* 1ED Rsvd for IER (if ne */
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u8 ier; /* 1EE Interrupt Enable */
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u8 isr; /* 1EF Input Signal Reg */
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u8 osr; /* 1F0 Output Signal Reg */
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u8 reset; /* 1F1 Reset/Reload Reg */
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u8 disable; /* 1F2 Disable Reg */
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u8 sync; /* 1F3 Sync Reg */
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u8 error_stat; /* 1F4 Error Status */
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u8 cable_id; /* 1F5 Cable ID */
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u8 cs_length; /* 1F6 CS Load Length */
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u8 mac_length; /* 1F7 Mac Load Length */
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u32 cs_load_addr; /* 1F8-1FB Call Load PCI Addr */
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u32 mac_load_addr; /* 1FC-1FF Mac Load PCI Addr */
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};
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/*
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* adapter defines and structures
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*/
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#define ICOM_CONTROL_START_A 0x00000008
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#define ICOM_CONTROL_STOP_A 0x00000004
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#define ICOM_CONTROL_START_B 0x00000002
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#define ICOM_CONTROL_STOP_B 0x00000001
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#define ICOM_CONTROL_START_C 0x00000008
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#define ICOM_CONTROL_STOP_C 0x00000004
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#define ICOM_CONTROL_START_D 0x00000002
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#define ICOM_CONTROL_STOP_D 0x00000001
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#define ICOM_IRAM_OFFSET 0x1000
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#define ICOM_IRAM_SIZE 0x0C00
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#define ICOM_DCE_IRAM_OFFSET 0x0A00
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#define ICOM_CABLE_ID_VALID 0x01
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#define ICOM_CABLE_ID_MASK 0xF0
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#define ICOM_DISABLE 0x80
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#define CMD_XMIT_RCV_ENABLE 0xC0
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#define CMD_XMIT_ENABLE 0x40
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#define CMD_RCV_DISABLE 0x00
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#define CMD_RCV_ENABLE 0x80
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#define CMD_RESTART 0x01
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#define CMD_HOLD_XMIT 0x02
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#define CMD_SND_BREAK 0x04
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#define RS232_CABLE 0x06
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#define V24_CABLE 0x0E
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#define V35_CABLE 0x0C
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#define V36_CABLE 0x02
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#define NO_CABLE 0x00
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#define START_DOWNLOAD 0x80
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#define ICOM_INT_MASK_PRC_A 0x00003FFF
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#define ICOM_INT_MASK_PRC_B 0x3FFF0000
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#define ICOM_INT_MASK_PRC_C 0x00003FFF
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#define ICOM_INT_MASK_PRC_D 0x3FFF0000
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#define INT_RCV_COMPLETED 0x1000
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#define INT_XMIT_COMPLETED 0x2000
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#define INT_IDLE_DETECT 0x0800
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#define INT_RCV_DISABLED 0x0400
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#define INT_XMIT_DISABLED 0x0200
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#define INT_RCV_XMIT_SHUTDOWN 0x0100
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#define INT_FATAL_ERROR 0x0080
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#define INT_CABLE_PULL 0x0020
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#define INT_SIGNAL_CHANGE 0x0010
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#define HDLC_PPP_PURE_ASYNC 0x02
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#define HDLC_FF_FILL 0x00
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#define HDLC_HDW_FLOW 0x01
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#define START_XMIT 0x80
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#define ICOM_ACFG_DRIVE1 0x20
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#define ICOM_ACFG_NO_PARITY 0x00
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#define ICOM_ACFG_PARITY_ENAB 0x02
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#define ICOM_ACFG_PARITY_ODD 0x01
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#define ICOM_ACFG_8BPC 0x00
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#define ICOM_ACFG_7BPC 0x04
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#define ICOM_ACFG_6BPC 0x08
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#define ICOM_ACFG_5BPC 0x0C
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#define ICOM_ACFG_1STOP_BIT 0x00
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#define ICOM_ACFG_2STOP_BIT 0x10
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#define ICOM_DTR 0x80
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#define ICOM_RTS 0x40
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#define ICOM_RI 0x08
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#define ICOM_DSR 0x80
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#define ICOM_DCD 0x20
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#define ICOM_CTS 0x40
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#define NUM_XBUFFS 1
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#define NUM_RBUFFS 2
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#define RCV_BUFF_SZ 0x0200
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#define XMIT_BUFF_SZ 0x1000
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struct statusArea {
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/**********************************************/
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/* Transmit Status Area */
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/**********************************************/
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struct xmit_status_area{
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u32 leNext; /* Next entry in Little Endian on Adapter */
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u32 leNextASD;
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u32 leBuffer; /* Buffer for entry in LE for Adapter */
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u16 leLengthASD;
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u16 leOffsetASD;
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u16 leLength; /* Length of data in segment */
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u16 flags;
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#define SA_FLAGS_DONE 0x0080 /* Done with Segment */
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#define SA_FLAGS_CONTINUED 0x8000 /* More Segments */
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#define SA_FLAGS_IDLE 0x4000 /* Mark IDLE after frm */
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#define SA_FLAGS_READY_TO_XMIT 0x0800
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#define SA_FLAGS_STAT_MASK 0x007F
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} xmit[NUM_XBUFFS];
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/**********************************************/
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/* Receive Status Area */
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/**********************************************/
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struct {
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u32 leNext; /* Next entry in Little Endian on Adapter */
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u32 leNextASD;
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u32 leBuffer; /* Buffer for entry in LE for Adapter */
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u16 WorkingLength; /* size of segment */
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u16 reserv01;
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u16 leLength; /* Length of data in segment */
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u16 flags;
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#define SA_FL_RCV_DONE 0x0010 /* Data ready */
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#define SA_FLAGS_OVERRUN 0x0040
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#define SA_FLAGS_PARITY_ERROR 0x0080
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#define SA_FLAGS_FRAME_ERROR 0x0001
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#define SA_FLAGS_FRAME_TRUNC 0x0002
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#define SA_FLAGS_BREAK_DET 0x0004 /* set conditionally by device driver, not hardware */
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#define SA_FLAGS_RCV_MASK 0xFFE6
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} rcv[NUM_RBUFFS];
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};
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struct icom_adapter;
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#define ICOM_MAJOR 243
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#define ICOM_MINOR_START 0
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struct icom_port {
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struct uart_port uart_port;
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u8 imbed_modem;
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#define ICOM_UNKNOWN 1
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#define ICOM_RVX 2
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#define ICOM_IMBED_MODEM 3
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unsigned char cable_id;
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unsigned char read_status_mask;
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unsigned char ignore_status_mask;
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void __iomem * int_reg;
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struct icom_regs __iomem *global_reg;
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struct func_dram __iomem *dram;
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int port;
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struct statusArea *statStg;
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dma_addr_t statStg_pci;
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u32 *xmitRestart;
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dma_addr_t xmitRestart_pci;
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unsigned char *xmit_buf;
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dma_addr_t xmit_buf_pci;
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unsigned char *recv_buf;
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dma_addr_t recv_buf_pci;
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int next_rcv;
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int put_length;
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int status;
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#define ICOM_PORT_ACTIVE 1 /* Port exists. */
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#define ICOM_PORT_OFF 0 /* Port does not exist. */
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int load_in_progress;
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struct icom_adapter *adapter;
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};
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struct icom_adapter {
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void __iomem * base_addr;
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unsigned long base_addr_pci;
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struct pci_dev *pci_dev;
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struct icom_port port_info[4];
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int index;
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int version;
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#define ADAPTER_V1 0x0001
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#define ADAPTER_V2 0x0002
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u32 subsystem_id;
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#define FOUR_PORT_MODEL 0x0252
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#define V2_TWO_PORTS_RVX 0x021A
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#define V2_ONE_PORT_RVX_ONE_PORT_IMBED_MDM 0x0251
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int numb_ports;
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struct list_head icom_adapter_entry;
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struct kref kref;
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};
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/* prototype */
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extern void iCom_sercons_init(void);
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struct lookup_proc_table {
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u32 __iomem *global_control_reg;
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unsigned long processor_id;
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};
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struct lookup_int_table {
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u32 __iomem *global_int_mask;
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unsigned long processor_id;
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};
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