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246da26d37
Presently there are three peripherals that gets it timing by runtime calculation. Those peripherals can work with frequency scaling that affects gpmc clock. But timing calculation for them are in different ways. Here a generic runtime calculation method is proposed. Input to this function were selected so that they represent timing variables that are present in peripheral datasheets. Motive behind this was to achieve DT bindings for the inputs as is. Even though a few of the tusb6010 timings could not be made directly related to timings normally found on peripherals, expressions used were translated to those that could be justified. There are possibilities of improving the calculations, like calculating timing for read & write operations in a more similar way. Expressions derived here were tested for async onenand on omap3evm (as vanilla Kernel does not have omap3evm onenand support, local patch was used). Other peripherals, tusb6010, smc91x calculations were validated by simulating on omap3evm. Regarding "we_on" for onenand async, it was found that even for muxed address/data, it need not be greater than "adv_wr_off", but rather could be derived from write setup time for peripheral from start of access time, hence would more be in line with peripheral timings. With this method it was working fine. If it is required in some cases to have "we_on" same as "wr_data_mux_bus" (i.e. greater than "adv_wr_off"), another variable could be added to indicate it. But such a requirement is not expected though. It has been observed that "adv_rd_off" & "adv_wr_off" are currently calculated by adding an offset over "oe_on" and "we_on" respectively in the case of smc91x. But peripheral datasheet does not specify so and so "adv_rd(wr)_off" has been derived (to be specific, made ignorant of "oe_on" and "we_on") observing datasheet rather than adding an offset. Hence this generic routine is expected to work for smc91x (91C96 RX51 board). This was verified on smsc911x (9220 on OMAP3EVM) - a similar ethernet controller. Timings are calculated in ps to prevent rounding errors and converted to ns at final stage so that these values can be directly fed to gpmc_cs_set_timings(). gpmc_cs_set_timings() would be modified to take ps once all custom timing routines are replaced by the generic routine, at the same time generic timing routine would be modified to provide timings in ps. struct gpmc_timings field types are upgraded from u16 => u32 so that it can hold ps values. Whole of this exercise is being done to achieve driver and DT conversion. If timings could not be calculated in a peripheral agnostic way, either gpmc driver would have to be peripheral gnostic or a wrapper arrangement over gpmc driver would be required. Signed-off-by: Afzal Mohammed <afzal@ti.com>
217 lines
7.5 KiB
C
217 lines
7.5 KiB
C
/*
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* General-Purpose Memory Controller for OMAP2
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*
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* Copyright (C) 2005-2006 Nokia Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __OMAP2_GPMC_H
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#define __OMAP2_GPMC_H
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#include <linux/platform_data/mtd-nand-omap2.h>
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/* Maximum Number of Chip Selects */
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#define GPMC_CS_NUM 8
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#define GPMC_CS_CONFIG1 0x00
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#define GPMC_CS_CONFIG2 0x04
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#define GPMC_CS_CONFIG3 0x08
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#define GPMC_CS_CONFIG4 0x0c
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#define GPMC_CS_CONFIG5 0x10
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#define GPMC_CS_CONFIG6 0x14
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#define GPMC_CS_CONFIG7 0x18
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#define GPMC_CS_NAND_COMMAND 0x1c
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#define GPMC_CS_NAND_ADDRESS 0x20
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#define GPMC_CS_NAND_DATA 0x24
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/* Control Commands */
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#define GPMC_CONFIG_RDY_BSY 0x00000001
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#define GPMC_CONFIG_DEV_SIZE 0x00000002
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#define GPMC_CONFIG_DEV_TYPE 0x00000003
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#define GPMC_SET_IRQ_STATUS 0x00000004
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#define GPMC_CONFIG_WP 0x00000005
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#define GPMC_ENABLE_IRQ 0x0000000d
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/* ECC commands */
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#define GPMC_ECC_READ 0 /* Reset Hardware ECC for read */
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#define GPMC_ECC_WRITE 1 /* Reset Hardware ECC for write */
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#define GPMC_ECC_READSYN 2 /* Reset before syndrom is read back */
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#define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31)
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#define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30)
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#define GPMC_CONFIG1_READTYPE_ASYNC (0 << 29)
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#define GPMC_CONFIG1_READTYPE_SYNC (1 << 29)
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#define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28)
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#define GPMC_CONFIG1_WRITETYPE_ASYNC (0 << 27)
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#define GPMC_CONFIG1_WRITETYPE_SYNC (1 << 27)
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#define GPMC_CONFIG1_CLKACTIVATIONTIME(val) ((val & 3) << 25)
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#define GPMC_CONFIG1_PAGE_LEN(val) ((val & 3) << 23)
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#define GPMC_CONFIG1_WAIT_READ_MON (1 << 22)
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#define GPMC_CONFIG1_WAIT_WRITE_MON (1 << 21)
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#define GPMC_CONFIG1_WAIT_MON_IIME(val) ((val & 3) << 18)
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#define GPMC_CONFIG1_WAIT_PIN_SEL(val) ((val & 3) << 16)
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#define GPMC_CONFIG1_DEVICESIZE(val) ((val & 3) << 12)
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#define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1)
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#define GPMC_CONFIG1_DEVICETYPE(val) ((val & 3) << 10)
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#define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0)
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#define GPMC_CONFIG1_MUXADDDATA (1 << 9)
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#define GPMC_CONFIG1_TIME_PARA_GRAN (1 << 4)
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#define GPMC_CONFIG1_FCLK_DIV(val) (val & 3)
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#define GPMC_CONFIG1_FCLK_DIV2 (GPMC_CONFIG1_FCLK_DIV(1))
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#define GPMC_CONFIG1_FCLK_DIV3 (GPMC_CONFIG1_FCLK_DIV(2))
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#define GPMC_CONFIG1_FCLK_DIV4 (GPMC_CONFIG1_FCLK_DIV(3))
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#define GPMC_CONFIG7_CSVALID (1 << 6)
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#define GPMC_DEVICETYPE_NOR 0
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#define GPMC_DEVICETYPE_NAND 2
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#define GPMC_CONFIG_WRITEPROTECT 0x00000010
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#define WR_RD_PIN_MONITORING 0x00600000
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#define GPMC_IRQ_FIFOEVENTENABLE 0x01
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#define GPMC_IRQ_COUNT_EVENT 0x02
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/* bool type time settings */
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struct gpmc_bool_timings {
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bool cycle2cyclediffcsen;
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bool cycle2cyclesamecsen;
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bool we_extra_delay;
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bool oe_extra_delay;
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bool adv_extra_delay;
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bool cs_extra_delay;
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bool time_para_granularity;
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};
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/*
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* Note that all values in this struct are in nanoseconds except sync_clk
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* (which is in picoseconds), while the register values are in gpmc_fck cycles.
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*/
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struct gpmc_timings {
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/* Minimum clock period for synchronous mode (in picoseconds) */
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u32 sync_clk;
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/* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */
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u32 cs_on; /* Assertion time */
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u32 cs_rd_off; /* Read deassertion time */
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u32 cs_wr_off; /* Write deassertion time */
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/* ADV signal timings corresponding to GPMC_CONFIG3 */
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u32 adv_on; /* Assertion time */
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u32 adv_rd_off; /* Read deassertion time */
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u32 adv_wr_off; /* Write deassertion time */
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/* WE signals timings corresponding to GPMC_CONFIG4 */
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u32 we_on; /* WE assertion time */
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u32 we_off; /* WE deassertion time */
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/* OE signals timings corresponding to GPMC_CONFIG4 */
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u32 oe_on; /* OE assertion time */
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u32 oe_off; /* OE deassertion time */
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/* Access time and cycle time timings corresponding to GPMC_CONFIG5 */
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u32 page_burst_access; /* Multiple access word delay */
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u32 access; /* Start-cycle to first data valid delay */
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u32 rd_cycle; /* Total read cycle time */
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u32 wr_cycle; /* Total write cycle time */
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u32 bus_turnaround;
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u32 cycle2cycle_delay;
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u32 wait_monitoring;
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u32 clk_activation;
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/* The following are only on OMAP3430 */
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u32 wr_access; /* WRACCESSTIME */
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u32 wr_data_mux_bus; /* WRDATAONADMUXBUS */
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struct gpmc_bool_timings bool_timings;
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};
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/* Device timings in picoseconds */
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struct gpmc_device_timings {
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u32 t_ceasu; /* address setup to CS valid */
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u32 t_avdasu; /* address setup to ADV valid */
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/* XXX: try to combine t_avdp_r & t_avdp_w. Issue is
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* of tusb using these timings even for sync whilst
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* ideally for adv_rd/(wr)_off it should have considered
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* t_avdh instead. This indirectly necessitates r/w
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* variations of t_avdp as it is possible to have one
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* sync & other async
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*/
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u32 t_avdp_r; /* ADV low time (what about t_cer ?) */
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u32 t_avdp_w;
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u32 t_aavdh; /* address hold time */
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u32 t_oeasu; /* address setup to OE valid */
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u32 t_aa; /* access time from ADV assertion */
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u32 t_iaa; /* initial access time */
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u32 t_oe; /* access time from OE assertion */
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u32 t_ce; /* access time from CS asertion */
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u32 t_rd_cycle; /* read cycle time */
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u32 t_cez_r; /* read CS deassertion to high Z */
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u32 t_cez_w; /* write CS deassertion to high Z */
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u32 t_oez; /* OE deassertion to high Z */
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u32 t_weasu; /* address setup to WE valid */
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u32 t_wpl; /* write assertion time */
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u32 t_wph; /* write deassertion time */
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u32 t_wr_cycle; /* write cycle time */
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u32 clk;
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u32 t_bacc; /* burst access valid clock to output delay */
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u32 t_ces; /* CS setup time to clk */
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u32 t_avds; /* ADV setup time to clk */
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u32 t_avdh; /* ADV hold time from clk */
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u32 t_ach; /* address hold time from clk */
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u32 t_rdyo; /* clk to ready valid */
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u32 t_ce_rdyz; /* XXX: description ?, or use t_cez instead */
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u32 t_ce_avd; /* CS on to ADV on delay */
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/* XXX: check the possibility of combining
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* cyc_aavhd_oe & cyc_aavdh_we
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*/
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u8 cyc_aavdh_oe;/* read address hold time in cycles */
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u8 cyc_aavdh_we;/* write address hold time in cycles */
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u8 cyc_oe; /* access time from OE assertion in cycles */
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u8 cyc_wpl; /* write deassertion time in cycles */
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u32 cyc_iaa; /* initial access time in cycles */
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bool mux; /* address & data muxed */
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bool sync_write;/* synchronous write */
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bool sync_read; /* synchronous read */
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/* extra delays */
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bool ce_xdelay;
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bool avd_xdelay;
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bool oe_xdelay;
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bool we_xdelay;
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};
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extern int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
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struct gpmc_device_timings *dev_t);
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extern void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs);
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extern int gpmc_get_client_irq(unsigned irq_config);
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extern unsigned int gpmc_ns_to_ticks(unsigned int time_ns);
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extern unsigned int gpmc_ps_to_ticks(unsigned int time_ps);
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extern unsigned int gpmc_ticks_to_ns(unsigned int ticks);
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extern unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns);
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extern unsigned long gpmc_get_fclk_period(void);
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extern void gpmc_cs_write_reg(int cs, int idx, u32 val);
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extern u32 gpmc_cs_read_reg(int cs, int idx);
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extern int gpmc_calc_divider(unsigned int sync_clk);
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extern int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t);
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extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base);
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extern void gpmc_cs_free(int cs);
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extern int gpmc_cs_set_reserved(int cs, int reserved);
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extern int gpmc_cs_reserved(int cs);
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extern void omap3_gpmc_save_context(void);
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extern void omap3_gpmc_restore_context(void);
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extern int gpmc_cs_configure(int cs, int cmd, int wval);
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#endif
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