mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
212 lines
5.3 KiB
C
212 lines
5.3 KiB
C
/**
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* @file arch/alpha/oprofile/op_model_ev5.c
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*
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* @remark Copyright 2002 OProfile authors
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* @remark Read the file COPYING
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*
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* @author Richard Henderson <rth@twiddle.net>
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*/
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#include <linux/oprofile.h>
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#include <linux/init.h>
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#include <linux/smp.h>
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#include <asm/ptrace.h>
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#include <asm/system.h>
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#include "op_impl.h"
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/* Compute all of the registers in preparation for enabling profiling.
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The 21164 (EV5) and 21164PC (PCA65) vary in the bit placement and
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meaning of the "CBOX" events. Given that we don't care about meaning
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at this point, arrange for the difference in bit placement to be
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handled by common code. */
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static void
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common_reg_setup(struct op_register_config *reg,
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struct op_counter_config *ctr,
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struct op_system_config *sys,
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int cbox1_ofs, int cbox2_ofs)
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{
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int i, ctl, reset, need_reset;
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/* Select desired events. The event numbers are selected such
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that they map directly into the event selection fields:
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PCSEL0: 0, 1
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PCSEL1: 24-39
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CBOX1: 40-47
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PCSEL2: 48-63
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CBOX2: 64-71
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There are two special cases, in that CYCLES can be measured
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on PCSEL[02], and SCACHE_WRITE can be measured on CBOX[12].
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These event numbers are canonicalizes to their first appearance. */
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ctl = 0;
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for (i = 0; i < 3; ++i) {
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unsigned long event = ctr[i].event;
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if (!ctr[i].enabled)
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continue;
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/* Remap the duplicate events, as described above. */
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if (i == 2) {
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if (event == 0)
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event = 12+48;
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else if (event == 2+41)
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event = 4+65;
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}
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/* Convert the event numbers onto mux_select bit mask. */
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if (event < 2)
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ctl |= event << 31;
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else if (event < 24)
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/* error */;
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else if (event < 40)
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ctl |= (event - 24) << 4;
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else if (event < 48)
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ctl |= (event - 40) << cbox1_ofs | 15 << 4;
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else if (event < 64)
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ctl |= event - 48;
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else if (event < 72)
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ctl |= (event - 64) << cbox2_ofs | 15;
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}
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reg->mux_select = ctl;
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/* Select processor mode. */
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/* ??? Need to come up with some mechanism to trace only selected
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processes. For now select from pal, kernel and user mode. */
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ctl = 0;
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ctl |= !sys->enable_pal << 9;
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ctl |= !sys->enable_kernel << 8;
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ctl |= !sys->enable_user << 30;
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reg->proc_mode = ctl;
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/* Select interrupt frequencies. Take the interrupt count selected
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by the user, and map it onto one of the possible counter widths.
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If the user value is in between, compute a value to which the
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counter is reset at each interrupt. */
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ctl = reset = need_reset = 0;
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for (i = 0; i < 3; ++i) {
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unsigned long max, hilo, count = ctr[i].count;
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if (!ctr[i].enabled)
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continue;
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if (count <= 256)
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count = 256, hilo = 3, max = 256;
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else {
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max = (i == 2 ? 16384 : 65536);
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hilo = 2;
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if (count > max)
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count = max;
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}
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ctr[i].count = count;
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ctl |= hilo << (8 - i*2);
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reset |= (max - count) << (48 - 16*i);
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if (count != max)
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need_reset |= 1 << i;
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}
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reg->freq = ctl;
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reg->reset_values = reset;
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reg->need_reset = need_reset;
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}
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static void
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ev5_reg_setup(struct op_register_config *reg,
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struct op_counter_config *ctr,
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struct op_system_config *sys)
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{
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common_reg_setup(reg, ctr, sys, 19, 22);
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}
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static void
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pca56_reg_setup(struct op_register_config *reg,
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struct op_counter_config *ctr,
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struct op_system_config *sys)
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{
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common_reg_setup(reg, ctr, sys, 8, 11);
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}
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/* Program all of the registers in preparation for enabling profiling. */
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static void
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ev5_cpu_setup (void *x)
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{
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struct op_register_config *reg = x;
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wrperfmon(2, reg->mux_select);
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wrperfmon(3, reg->proc_mode);
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wrperfmon(4, reg->freq);
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wrperfmon(6, reg->reset_values);
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}
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/* CTR is a counter for which the user has requested an interrupt count
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in between one of the widths selectable in hardware. Reset the count
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for CTR to the value stored in REG->RESET_VALUES.
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For EV5, this means disabling profiling, reading the current values,
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masking in the value for the desired register, writing, then turning
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profiling back on.
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This can be streamlined if profiling is only enabled for user mode.
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In that case we know that the counters are not currently incrementing
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(due to being in kernel mode). */
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static void
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ev5_reset_ctr(struct op_register_config *reg, unsigned long ctr)
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{
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unsigned long values, mask, not_pk, reset_values;
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mask = (ctr == 0 ? 0xfffful << 48
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: ctr == 1 ? 0xfffful << 32
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: 0x3fff << 16);
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not_pk = 1 << 9 | 1 << 8;
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reset_values = reg->reset_values;
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if ((reg->proc_mode & not_pk) == not_pk) {
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values = wrperfmon(5, 0);
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values = (reset_values & mask) | (values & ~mask & -2);
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wrperfmon(6, values);
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} else {
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wrperfmon(0, -1);
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values = wrperfmon(5, 0);
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values = (reset_values & mask) | (values & ~mask & -2);
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wrperfmon(6, values);
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wrperfmon(1, reg->enable);
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}
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}
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static void
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ev5_handle_interrupt(unsigned long which, struct pt_regs *regs,
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struct op_counter_config *ctr)
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{
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/* Record the sample. */
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oprofile_add_sample(regs, which);
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}
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struct op_axp_model op_model_ev5 = {
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.reg_setup = ev5_reg_setup,
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.cpu_setup = ev5_cpu_setup,
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.reset_ctr = ev5_reset_ctr,
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.handle_interrupt = ev5_handle_interrupt,
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.cpu_type = "alpha/ev5",
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.num_counters = 3,
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.can_set_proc_mode = 1,
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};
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struct op_axp_model op_model_pca56 = {
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.reg_setup = pca56_reg_setup,
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.cpu_setup = ev5_cpu_setup,
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.reset_ctr = ev5_reset_ctr,
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.handle_interrupt = ev5_handle_interrupt,
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.cpu_type = "alpha/pca56",
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.num_counters = 3,
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.can_set_proc_mode = 1,
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};
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