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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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8efcf34a26
This is a branch with a few merge requests that either came in late, or took a while longer for us to review and merge than usual and thus cut it a bit close to the merge window. We stage them in a separate branch and if things look good, we still send them up -- and that's the case here. This is mostly DT additions for Renesas platforms, adding IP block descriptions for existing and new SoCs. There are also some driver updates for Qualcomm platforms for SMEM/QMI and GENI, which is their generalized serial protocol interface. -----BEGIN PGP SIGNATURE----- iQJDBAABCAAtFiEElf+HevZ4QCAJmMQ+jBrnPN6EHHcFAlsfCVIPHG9sb2ZAbGl4 b20ubmV0AAoJEIwa5zzehBx3KOcP/3O2+igstXt5rhemITdyi8rHkrIHPgetf25e ISBQzYrQOHV21SqT4le/Gk2CCQ6iX5Nv2DYoIrCzFWi/4DoDxXvryczQLla02Nru i8fcuxae7aFGW7/97G1+cATGPwuBLPiKXs6Wj01sKHeLBja5Det7eoXuHag7Y/Lo 4ls9wNZybMdlCcGm6+ULdj+XUdRyYUhOQQYvnPm2Q8hEkM+AiwLOBJTFwef9P5ad mX37kPDfwCxYwQXgZB1RkK/oJu0G2mTZXmGH5o+s+9yAyAupCQhmHGOrt3mlOf7j tLRlSgarJlO/QGIpJmDuCcxt3msD3OMd2dPbdgwojdpvycOU8EVWYLmCRpyIWQXv DCv9A9Gp4KlJnwxheVegBtilRA1aKsGuarWq6yeyOFt8N23Bgg/IjYKI9JF5+hPD M4q1oVAbUlfWb79rEc+TB0d7euREBkNn4TzzKMSOyP3eGUrXR0WUlq2A2VLxgIJo cx/ufY7CwvRgV+VxfhRbca+FmwDnu7uqzwLe73Ys2hnsuv8hXEtc+vSybqKqxVeU nHpWAqwaWhijlJiGq722vPo8avrLwjsxRwimogvijtesz9ZlTqrGtjkg61+eN2h8 eeuyRAsMUfVRiKuL3W+q4s0rzIauormnKsvRScKVyNFuiJfrfYb1odLoDGaOV/9G dQ7hA7TW =RUL0 -----END PGP SIGNATURE----- Merge tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC late updates from Olof Johansson: "This is a branch with a few merge requests that either came in late, or took a while longer for us to review and merge than usual and thus cut it a bit close to the merge window. We stage them in a separate branch and if things look good, we still send them up -- and that's the case here. This is mostly DT additions for Renesas platforms, adding IP block descriptions for existing and new SoCs. There are also some driver updates for Qualcomm platforms for SMEM/QMI and GENI, which is their generalized serial protocol interface" * tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (186 commits) soc: qcom: smem: introduce qcom_smem_virt_to_phys() soc: qcom: qmi: fix a buffer sizing bug MAINTAINERS: Update pattern for qcom_scm soc: Unconditionally include qcom Makefile soc: qcom: smem: check sooner in qcom_smem_set_global_partition() soc: qcom: smem: fix qcom_smem_set_global_partition() soc: qcom: smem: fix off-by-one error in qcom_smem_alloc_private() soc: qcom: smem: byte swap values properly soc: qcom: smem: return proper type for cached entry functions soc: qcom: smem: fix first cache entry calculation soc: qcom: cmd-db: Make endian-agnostic drivers: qcom: add command DB driver arm64: dts: renesas: salvator-common: Add ADV7482 support ARM: dts: r8a7740: Add CEU1 ARM: dts: r8a7740: Add CEU0 arm64: dts: renesas: salvator-common: enable VIN arm64: dts: renesas: r8a77970: add VIN and CSI-2 nodes arm64: dts: renesas: r8a77965: add VIN and CSI-2 nodes arm64: dts: renesas: r8a7796: add VIN and CSI-2 nodes arm64: dts: renesas: r8a7795-es1: add CSI-2 node ...
1457 lines
42 KiB
Plaintext
1457 lines
42 KiB
Plaintext
/*
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* Device Tree Source for the r8a7793 SoC
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*
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* Copyright (C) 2014-2015 Renesas Electronics Corporation
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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#include <dt-bindings/clock/r8a7793-cpg-mssr.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/power/r8a7793-sysc.h>
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/ {
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compatible = "renesas,r8a7793";
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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i2c2 = &i2c2;
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i2c3 = &i2c3;
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i2c4 = &i2c4;
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i2c5 = &i2c5;
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i2c6 = &i2c6;
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i2c7 = &i2c7;
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i2c8 = &i2c8;
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spi0 = &qspi;
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};
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/*
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* The external audio clocks are configured as 0 Hz fixed frequency
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* clocks by default.
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* Boards that provide audio clocks should override them.
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*/
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audio_clk_a: audio_clk_a {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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audio_clk_b: audio_clk_b {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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audio_clk_c: audio_clk_c {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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/* External CAN clock */
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can_clk: can {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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/* This value must be overridden by the board. */
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clock-frequency = <0>;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "renesas,apmu";
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0>;
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clock-frequency = <1500000000>;
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voltage-tolerance = <1>; /* 1% */
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clocks = <&cpg CPG_CORE R8A7793_CLK_Z>;
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clock-latency = <300000>; /* 300 us */
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power-domains = <&sysc R8A7793_PD_CA15_CPU0>;
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/* kHz - uV - OPPs unknown yet */
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operating-points = <1500000 1000000>,
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<1312500 1000000>,
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<1125000 1000000>,
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< 937500 1000000>,
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< 750000 1000000>,
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< 375000 1000000>;
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next-level-cache = <&L2_CA15>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <1>;
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clock-frequency = <1500000000>;
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clocks = <&cpg CPG_CORE R8A7793_CLK_Z>;
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power-domains = <&sysc R8A7793_PD_CA15_CPU1>;
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};
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L2_CA15: cache-controller-0 {
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compatible = "cache";
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power-domains = <&sysc R8A7793_PD_CA15_SCU>;
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cache-unified;
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cache-level = <2>;
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};
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};
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/* External root clock */
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extal_clk: extal {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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/* This value must be overridden by the board. */
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clock-frequency = <0>;
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};
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pmu {
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compatible = "arm,cortex-a15-pmu";
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interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
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<&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&cpu0>, <&cpu1>;
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};
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/* External SCIF clock */
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scif_clk: scif {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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/* This value must be overridden by the board. */
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clock-frequency = <0>;
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};
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soc {
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compatible = "simple-bus";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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rwdt: watchdog@e6020000 {
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compatible = "renesas,r8a7793-wdt",
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"renesas,rcar-gen2-wdt";
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reg = <0 0xe6020000 0 0x0c>;
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clocks = <&cpg CPG_MOD 402>;
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power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
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resets = <&cpg 402>;
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status = "disabled";
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};
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gpio0: gpio@e6050000 {
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compatible = "renesas,gpio-r8a7793",
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"renesas,rcar-gen2-gpio";
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reg = <0 0xe6050000 0 0x50>;
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interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 0 32>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&cpg CPG_MOD 912>;
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power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
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resets = <&cpg 912>;
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};
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gpio1: gpio@e6051000 {
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compatible = "renesas,gpio-r8a7793",
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"renesas,rcar-gen2-gpio";
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reg = <0 0xe6051000 0 0x50>;
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interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 32 26>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&cpg CPG_MOD 911>;
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power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
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resets = <&cpg 911>;
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};
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gpio2: gpio@e6052000 {
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compatible = "renesas,gpio-r8a7793",
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"renesas,rcar-gen2-gpio";
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reg = <0 0xe6052000 0 0x50>;
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interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 64 32>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&cpg CPG_MOD 910>;
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power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
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resets = <&cpg 910>;
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};
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gpio3: gpio@e6053000 {
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compatible = "renesas,gpio-r8a7793",
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"renesas,rcar-gen2-gpio";
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reg = <0 0xe6053000 0 0x50>;
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interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 96 32>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&cpg CPG_MOD 909>;
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power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
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resets = <&cpg 909>;
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};
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gpio4: gpio@e6054000 {
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compatible = "renesas,gpio-r8a7793",
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"renesas,rcar-gen2-gpio";
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reg = <0 0xe6054000 0 0x50>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 128 32>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&cpg CPG_MOD 908>;
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power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
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resets = <&cpg 908>;
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};
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gpio5: gpio@e6055000 {
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compatible = "renesas,gpio-r8a7793",
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"renesas,rcar-gen2-gpio";
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reg = <0 0xe6055000 0 0x50>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 160 32>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&cpg CPG_MOD 907>;
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power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
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resets = <&cpg 907>;
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};
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gpio6: gpio@e6055400 {
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compatible = "renesas,gpio-r8a7793",
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"renesas,rcar-gen2-gpio";
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reg = <0 0xe6055400 0 0x50>;
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interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 192 32>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&cpg CPG_MOD 905>;
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power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
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resets = <&cpg 905>;
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};
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gpio7: gpio@e6055800 {
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compatible = "renesas,gpio-r8a7793",
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"renesas,rcar-gen2-gpio";
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reg = <0 0xe6055800 0 0x50>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 224 26>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&cpg CPG_MOD 904>;
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power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
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resets = <&cpg 904>;
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};
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pfc: pin-controller@e6060000 {
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compatible = "renesas,pfc-r8a7793";
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reg = <0 0xe6060000 0 0x250>;
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};
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/* Special CPG clocks */
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cpg: clock-controller@e6150000 {
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compatible = "renesas,r8a7793-cpg-mssr";
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reg = <0 0xe6150000 0 0x1000>;
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clocks = <&extal_clk>, <&usb_extal_clk>;
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clock-names = "extal", "usb_extal";
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#clock-cells = <2>;
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#power-domain-cells = <0>;
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#reset-cells = <1>;
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};
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apmu@e6152000 {
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compatible = "renesas,r8a7793-apmu", "renesas,apmu";
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reg = <0 0xe6152000 0 0x188>;
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cpus = <&cpu0 &cpu1>;
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};
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rst: reset-controller@e6160000 {
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compatible = "renesas,r8a7793-rst";
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reg = <0 0xe6160000 0 0x0100>;
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};
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sysc: system-controller@e6180000 {
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compatible = "renesas,r8a7793-sysc";
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reg = <0 0xe6180000 0 0x0200>;
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#power-domain-cells = <1>;
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};
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irqc0: interrupt-controller@e61c0000 {
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compatible = "renesas,irqc-r8a7793", "renesas,irqc";
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#interrupt-cells = <2>;
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interrupt-controller;
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reg = <0 0xe61c0000 0 0x200>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 407>;
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power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
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resets = <&cpg 407>;
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};
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thermal: thermal@e61f0000 {
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compatible = "renesas,thermal-r8a7793",
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"renesas,rcar-gen2-thermal",
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"renesas,rcar-thermal";
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reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>;
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interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 522>;
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power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
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resets = <&cpg 522>;
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#thermal-sensor-cells = <0>;
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};
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ipmmu_sy0: mmu@e6280000 {
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compatible = "renesas,ipmmu-r8a7793",
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"renesas,ipmmu-vmsa";
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reg = <0 0xe6280000 0 0x1000>;
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interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
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#iommu-cells = <1>;
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status = "disabled";
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};
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ipmmu_sy1: mmu@e6290000 {
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compatible = "renesas,ipmmu-r8a7793",
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"renesas,ipmmu-vmsa";
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reg = <0 0xe6290000 0 0x1000>;
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interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
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#iommu-cells = <1>;
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status = "disabled";
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};
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ipmmu_ds: mmu@e6740000 {
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compatible = "renesas,ipmmu-r8a7793",
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"renesas,ipmmu-vmsa";
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reg = <0 0xe6740000 0 0x1000>;
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interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
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#iommu-cells = <1>;
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status = "disabled";
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};
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ipmmu_mp: mmu@ec680000 {
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compatible = "renesas,ipmmu-r8a7793",
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"renesas,ipmmu-vmsa";
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reg = <0 0xec680000 0 0x1000>;
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interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
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#iommu-cells = <1>;
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status = "disabled";
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};
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ipmmu_mx: mmu@fe951000 {
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compatible = "renesas,ipmmu-r8a7793",
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"renesas,ipmmu-vmsa";
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reg = <0 0xfe951000 0 0x1000>;
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interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
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#iommu-cells = <1>;
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status = "disabled";
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};
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ipmmu_rt: mmu@ffc80000 {
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compatible = "renesas,ipmmu-r8a7793",
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"renesas,ipmmu-vmsa";
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reg = <0 0xffc80000 0 0x1000>;
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interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
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#iommu-cells = <1>;
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status = "disabled";
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};
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ipmmu_gp: mmu@e62a0000 {
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compatible = "renesas,ipmmu-r8a7793",
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"renesas,ipmmu-vmsa";
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reg = <0 0xe62a0000 0 0x1000>;
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interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
|
|
#iommu-cells = <1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
icram0: sram@e63a0000 {
|
|
compatible = "mmio-sram";
|
|
reg = <0 0xe63a0000 0 0x12000>;
|
|
};
|
|
|
|
icram1: sram@e63c0000 {
|
|
compatible = "mmio-sram";
|
|
reg = <0 0xe63c0000 0 0x1000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0 0xe63c0000 0x1000>;
|
|
|
|
smp-sram@0 {
|
|
compatible = "renesas,smp-sram";
|
|
reg = <0 0x100>;
|
|
};
|
|
};
|
|
|
|
/* The memory map in the User's Manual maps the cores to
|
|
* bus numbers
|
|
*/
|
|
i2c0: i2c@e6508000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "renesas,i2c-r8a7793",
|
|
"renesas,rcar-gen2-i2c";
|
|
reg = <0 0xe6508000 0 0x40>;
|
|
interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 931>;
|
|
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
|
resets = <&cpg 931>;
|
|
i2c-scl-internal-delay-ns = <6>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c1: i2c@e6518000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "renesas,i2c-r8a7793",
|
|
"renesas,rcar-gen2-i2c";
|
|
reg = <0 0xe6518000 0 0x40>;
|
|
interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 930>;
|
|
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
|
resets = <&cpg 930>;
|
|
i2c-scl-internal-delay-ns = <6>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c2: i2c@e6530000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "renesas,i2c-r8a7793",
|
|
"renesas,rcar-gen2-i2c";
|
|
reg = <0 0xe6530000 0 0x40>;
|
|
interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 929>;
|
|
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
|
resets = <&cpg 929>;
|
|
i2c-scl-internal-delay-ns = <6>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c3: i2c@e6540000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "renesas,i2c-r8a7793",
|
|
"renesas,rcar-gen2-i2c";
|
|
reg = <0 0xe6540000 0 0x40>;
|
|
interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 928>;
|
|
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
|
resets = <&cpg 928>;
|
|
i2c-scl-internal-delay-ns = <6>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c4: i2c@e6520000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "renesas,i2c-r8a7793",
|
|
"renesas,rcar-gen2-i2c";
|
|
reg = <0 0xe6520000 0 0x40>;
|
|
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 927>;
|
|
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
|
resets = <&cpg 927>;
|
|
i2c-scl-internal-delay-ns = <6>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c5: i2c@e6528000 {
|
|
/* doesn't need pinmux */
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "renesas,i2c-r8a7793",
|
|
"renesas,rcar-gen2-i2c";
|
|
reg = <0 0xe6528000 0 0x40>;
|
|
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 925>;
|
|
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
|
resets = <&cpg 925>;
|
|
i2c-scl-internal-delay-ns = <110>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c6: i2c@e60b0000 {
|
|
/* doesn't need pinmux */
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "renesas,iic-r8a7793",
|
|
"renesas,rcar-gen2-iic",
|
|
"renesas,rmobile-iic";
|
|
reg = <0 0xe60b0000 0 0x425>;
|
|
interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 926>;
|
|
dmas = <&dmac0 0x77>, <&dmac0 0x78>,
|
|
<&dmac1 0x77>, <&dmac1 0x78>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
|
resets = <&cpg 926>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c7: i2c@e6500000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "renesas,iic-r8a7793",
|
|
"renesas,rcar-gen2-iic",
|
|
"renesas,rmobile-iic";
|
|
reg = <0 0xe6500000 0 0x425>;
|
|
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 318>;
|
|
dmas = <&dmac0 0x61>, <&dmac0 0x62>,
|
|
<&dmac1 0x61>, <&dmac1 0x62>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
|
resets = <&cpg 318>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c8: i2c@e6510000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "renesas,iic-r8a7793",
|
|
"renesas,rcar-gen2-iic",
|
|
"renesas,rmobile-iic";
|
|
reg = <0 0xe6510000 0 0x425>;
|
|
interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 323>;
|
|
dmas = <&dmac0 0x65>, <&dmac0 0x66>,
|
|
<&dmac1 0x65>, <&dmac1 0x66>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
|
resets = <&cpg 323>;
|
|
status = "disabled";
|
|
};
|
|
|
|
dmac0: dma-controller@e6700000 {
|
|
compatible = "renesas,dmac-r8a7793",
|
|
"renesas,rcar-dmac";
|
|
reg = <0 0xe6700000 0 0x20000>;
|
|
interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "error",
|
|
"ch0", "ch1", "ch2", "ch3",
|
|
"ch4", "ch5", "ch6", "ch7",
|
|
"ch8", "ch9", "ch10", "ch11",
|
|
"ch12", "ch13", "ch14";
|
|
clocks = <&cpg CPG_MOD 219>;
|
|
clock-names = "fck";
|
|
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
|
resets = <&cpg 219>;
|
|
#dma-cells = <1>;
|
|
dma-channels = <15>;
|
|
};
|
|
|
|
dmac1: dma-controller@e6720000 {
|
|
compatible = "renesas,dmac-r8a7793",
|
|
"renesas,rcar-dmac";
|
|
reg = <0 0xe6720000 0 0x20000>;
|
|
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "error",
|
|
"ch0", "ch1", "ch2", "ch3",
|
|
"ch4", "ch5", "ch6", "ch7",
|
|
"ch8", "ch9", "ch10", "ch11",
|
|
"ch12", "ch13", "ch14";
|
|
clocks = <&cpg CPG_MOD 218>;
|
|
clock-names = "fck";
|
|
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
|
resets = <&cpg 218>;
|
|
#dma-cells = <1>;
|
|
dma-channels = <15>;
|
|
};
|
|
|
|
qspi: spi@e6b10000 {
|
|
compatible = "renesas,qspi-r8a7793", "renesas,qspi";
|
|
reg = <0 0xe6b10000 0 0x2c>;
|
|
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 917>;
|
|
dmas = <&dmac0 0x17>, <&dmac0 0x18>,
|
|
<&dmac1 0x17>, <&dmac1 0x18>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
|
resets = <&cpg 917>;
|
|
num-cs = <1>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
scifa0: serial@e6c40000 {
|
|
compatible = "renesas,scifa-r8a7793",
|
|
"renesas,rcar-gen2-scifa", "renesas,scifa";
|
|
reg = <0 0xe6c40000 0 64>;
|
|
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 204>;
|
|
clock-names = "fck";
|
|
dmas = <&dmac0 0x21>, <&dmac0 0x22>,
|
|
<&dmac1 0x21>, <&dmac1 0x22>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
|
resets = <&cpg 204>;
|
|
status = "disabled";
|
|
};
|
|
|
|
scifa1: serial@e6c50000 {
|
|
compatible = "renesas,scifa-r8a7793",
|
|
"renesas,rcar-gen2-scifa", "renesas,scifa";
|
|
reg = <0 0xe6c50000 0 64>;
|
|
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 203>;
|
|
clock-names = "fck";
|
|
dmas = <&dmac0 0x25>, <&dmac0 0x26>,
|
|
<&dmac1 0x25>, <&dmac1 0x26>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
|
resets = <&cpg 203>;
|
|
status = "disabled";
|
|
};
|
|
|
|
scifa2: serial@e6c60000 {
|
|
compatible = "renesas,scifa-r8a7793",
|
|
"renesas,rcar-gen2-scifa", "renesas,scifa";
|
|
reg = <0 0xe6c60000 0 64>;
|
|
interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 202>;
|
|
clock-names = "fck";
|
|
dmas = <&dmac0 0x27>, <&dmac0 0x28>,
|
|
<&dmac1 0x27>, <&dmac1 0x28>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
|
resets = <&cpg 202>;
|
|
status = "disabled";
|
|
};
|
|
|
|
scifa3: serial@e6c70000 {
|
|
compatible = "renesas,scifa-r8a7793",
|
|
"renesas,rcar-gen2-scifa", "renesas,scifa";
|
|
reg = <0 0xe6c70000 0 64>;
|
|
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 1106>;
|
|
clock-names = "fck";
|
|
dmas = <&dmac0 0x1b>, <&dmac0 0x1c>,
|
|
<&dmac1 0x1b>, <&dmac1 0x1c>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
|
resets = <&cpg 1106>;
|
|
status = "disabled";
|
|
};
|
|
|
|
scifa4: serial@e6c78000 {
|
|
compatible = "renesas,scifa-r8a7793",
|
|
"renesas,rcar-gen2-scifa", "renesas,scifa";
|
|
reg = <0 0xe6c78000 0 64>;
|
|
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 1107>;
|
|
clock-names = "fck";
|
|
dmas = <&dmac0 0x1f>, <&dmac0 0x20>,
|
|
<&dmac1 0x1f>, <&dmac1 0x20>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
|
resets = <&cpg 1107>;
|
|
status = "disabled";
|
|
};
|
|
|
|
scifa5: serial@e6c80000 {
|
|
compatible = "renesas,scifa-r8a7793",
|
|
"renesas,rcar-gen2-scifa", "renesas,scifa";
|
|
reg = <0 0xe6c80000 0 64>;
|
|
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 1108>;
|
|
clock-names = "fck";
|
|
dmas = <&dmac0 0x23>, <&dmac0 0x24>,
|
|
<&dmac1 0x23>, <&dmac1 0x24>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
|
resets = <&cpg 1108>;
|
|
status = "disabled";
|
|
};
|
|
|
|
scifb0: serial@e6c20000 {
|
|
compatible = "renesas,scifb-r8a7793",
|
|
"renesas,rcar-gen2-scifb", "renesas,scifb";
|
|
reg = <0 0xe6c20000 0 0x100>;
|
|
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 206>;
|
|
clock-names = "fck";
|
|
dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
|
|
<&dmac1 0x3d>, <&dmac1 0x3e>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
|
resets = <&cpg 206>;
|
|
status = "disabled";
|
|
};
|
|
|
|
scifb1: serial@e6c30000 {
|
|
compatible = "renesas,scifb-r8a7793",
|
|
"renesas,rcar-gen2-scifb", "renesas,scifb";
|
|
reg = <0 0xe6c30000 0 0x100>;
|
|
interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 207>;
|
|
clock-names = "fck";
|
|
dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
|
|
<&dmac1 0x19>, <&dmac1 0x1a>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
|
resets = <&cpg 207>;
|
|
status = "disabled";
|
|
};
|
|
|
|
scifb2: serial@e6ce0000 {
|
|
compatible = "renesas,scifb-r8a7793",
|
|
"renesas,rcar-gen2-scifb", "renesas,scifb";
|
|
reg = <0 0xe6ce0000 0 0x100>;
|
|
interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 216>;
|
|
clock-names = "fck";
|
|
dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
|
|
<&dmac1 0x1d>, <&dmac1 0x1e>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
|
resets = <&cpg 216>;
|
|
status = "disabled";
|
|
};
|
|
|
|
scif0: serial@e6e60000 {
|
|
compatible = "renesas,scif-r8a7793",
|
|
"renesas,rcar-gen2-scif", "renesas,scif";
|
|
reg = <0 0xe6e60000 0 64>;
|
|
interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
|
|
<&scif_clk>;
|
|
clock-names = "fck", "brg_int", "scif_clk";
|
|
dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
|
|
<&dmac1 0x29>, <&dmac1 0x2a>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
|
resets = <&cpg 721>;
|
|
status = "disabled";
|
|
};
|
|
|
|
scif1: serial@e6e68000 {
|
|
compatible = "renesas,scif-r8a7793",
|
|
"renesas,rcar-gen2-scif", "renesas,scif";
|
|
reg = <0 0xe6e68000 0 64>;
|
|
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
|
|
<&scif_clk>;
|
|
clock-names = "fck", "brg_int", "scif_clk";
|
|
dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
|
|
<&dmac1 0x2d>, <&dmac1 0x2e>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
|
resets = <&cpg 720>;
|
|
status = "disabled";
|
|
};
|
|
|
|
scif2: serial@e6e58000 {
|
|
compatible = "renesas,scif-r8a7793",
|
|
"renesas,rcar-gen2-scif", "renesas,scif";
|
|
reg = <0 0xe6e58000 0 64>;
|
|
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 719>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
|
|
<&scif_clk>;
|
|
clock-names = "fck", "brg_int", "scif_clk";
|
|
dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
|
|
<&dmac1 0x2b>, <&dmac1 0x2c>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
|
resets = <&cpg 719>;
|
|
status = "disabled";
|
|
};
|
|
|
|
scif3: serial@e6ea8000 {
|
|
compatible = "renesas,scif-r8a7793",
|
|
"renesas,rcar-gen2-scif", "renesas,scif";
|
|
reg = <0 0xe6ea8000 0 64>;
|
|
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 718>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
|
|
<&scif_clk>;
|
|
clock-names = "fck", "brg_int", "scif_clk";
|
|
dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
|
|
<&dmac1 0x2f>, <&dmac1 0x30>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
|
resets = <&cpg 718>;
|
|
status = "disabled";
|
|
};
|
|
|
|
scif4: serial@e6ee0000 {
|
|
compatible = "renesas,scif-r8a7793",
|
|
"renesas,rcar-gen2-scif", "renesas,scif";
|
|
reg = <0 0xe6ee0000 0 64>;
|
|
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 715>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
|
|
<&scif_clk>;
|
|
clock-names = "fck", "brg_int", "scif_clk";
|
|
dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
|
|
<&dmac1 0xfb>, <&dmac1 0xfc>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
|
resets = <&cpg 715>;
|
|
status = "disabled";
|
|
};
|
|
|
|
scif5: serial@e6ee8000 {
|
|
compatible = "renesas,scif-r8a7793",
|
|
"renesas,rcar-gen2-scif", "renesas,scif";
|
|
reg = <0 0xe6ee8000 0 64>;
|
|
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 714>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
|
|
<&scif_clk>;
|
|
clock-names = "fck", "brg_int", "scif_clk";
|
|
dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
|
|
<&dmac1 0xfd>, <&dmac1 0xfe>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
|
resets = <&cpg 714>;
|
|
status = "disabled";
|
|
};
|
|
|
|
hscif0: serial@e62c0000 {
|
|
compatible = "renesas,hscif-r8a7793",
|
|
"renesas,rcar-gen2-hscif", "renesas,hscif";
|
|
reg = <0 0xe62c0000 0 96>;
|
|
interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 717>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
|
|
<&scif_clk>;
|
|
clock-names = "fck", "brg_int", "scif_clk";
|
|
dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
|
|
<&dmac1 0x39>, <&dmac1 0x3a>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
|
resets = <&cpg 717>;
|
|
status = "disabled";
|
|
};
|
|
|
|
hscif1: serial@e62c8000 {
|
|
compatible = "renesas,hscif-r8a7793",
|
|
"renesas,rcar-gen2-hscif", "renesas,hscif";
|
|
reg = <0 0xe62c8000 0 96>;
|
|
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 716>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
|
|
<&scif_clk>;
|
|
clock-names = "fck", "brg_int", "scif_clk";
|
|
dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
|
|
<&dmac1 0x4d>, <&dmac1 0x4e>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
|
resets = <&cpg 716>;
|
|
status = "disabled";
|
|
};
|
|
|
|
hscif2: serial@e62d0000 {
|
|
compatible = "renesas,hscif-r8a7793",
|
|
"renesas,rcar-gen2-hscif", "renesas,hscif";
|
|
reg = <0 0xe62d0000 0 96>;
|
|
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 713>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
|
|
<&scif_clk>;
|
|
clock-names = "fck", "brg_int", "scif_clk";
|
|
dmas = <&dmac0 0x3b>, <&dmac0 0x3c>,
|
|
<&dmac1 0x3b>, <&dmac1 0x3c>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
|
resets = <&cpg 713>;
|
|
status = "disabled";
|
|
};
|
|
|
|
can0: can@e6e80000 {
|
|
compatible = "renesas,can-r8a7793",
|
|
"renesas,rcar-gen2-can";
|
|
reg = <0 0xe6e80000 0 0x1000>;
|
|
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 916>, <&cpg CPG_CORE R8A7793_CLK_RCAN>,
|
|
<&can_clk>;
|
|
clock-names = "clkp1", "clkp2", "can_clk";
|
|
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
|
resets = <&cpg 916>;
|
|
status = "disabled";
|
|
};
|
|
|
|
can1: can@e6e88000 {
|
|
compatible = "renesas,can-r8a7793",
|
|
"renesas,rcar-gen2-can";
|
|
reg = <0 0xe6e88000 0 0x1000>;
|
|
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 915>, <&cpg CPG_CORE R8A7793_CLK_RCAN>,
|
|
<&can_clk>;
|
|
clock-names = "clkp1", "clkp2", "can_clk";
|
|
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
|
resets = <&cpg 915>;
|
|
status = "disabled";
|
|
};
|
|
|
|
vin0: video@e6ef0000 {
|
|
compatible = "renesas,vin-r8a7793",
|
|
"renesas,rcar-gen2-vin";
|
|
reg = <0 0xe6ef0000 0 0x1000>;
|
|
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 811>;
|
|
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
|
resets = <&cpg 811>;
|
|
status = "disabled";
|
|
};
|
|
|
|
vin1: video@e6ef1000 {
|
|
compatible = "renesas,vin-r8a7793",
|
|
"renesas,rcar-gen2-vin";
|
|
reg = <0 0xe6ef1000 0 0x1000>;
|
|
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 810>;
|
|
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
|
resets = <&cpg 810>;
|
|
status = "disabled";
|
|
};
|
|
|
|
vin2: video@e6ef2000 {
|
|
compatible = "renesas,vin-r8a7793",
|
|
"renesas,rcar-gen2-vin";
|
|
reg = <0 0xe6ef2000 0 0x1000>;
|
|
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 809>;
|
|
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
|
resets = <&cpg 809>;
|
|
status = "disabled";
|
|
};
|
|
|
|
rcar_sound: sound@ec500000 {
|
|
/*
|
|
* #sound-dai-cells is required
|
|
*
|
|
* Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
|
|
* Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
|
|
*/
|
|
compatible = "renesas,rcar_sound-r8a7793",
|
|
"renesas,rcar_sound-gen2";
|
|
reg = <0 0xec500000 0 0x1000>, /* SCU */
|
|
<0 0xec5a0000 0 0x100>, /* ADG */
|
|
<0 0xec540000 0 0x1000>, /* SSIU */
|
|
<0 0xec541000 0 0x280>, /* SSI */
|
|
<0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
|
|
reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
|
|
|
|
clocks = <&cpg CPG_MOD 1005>,
|
|
<&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
|
|
<&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
|
|
<&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
|
|
<&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
|
|
<&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
|
|
<&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
|
|
<&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
|
|
<&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
|
|
<&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
|
|
<&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
|
|
<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
|
|
<&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>,
|
|
<&cpg CPG_CORE R8A7793_CLK_M2>;
|
|
clock-names = "ssi-all",
|
|
"ssi.9", "ssi.8", "ssi.7", "ssi.6",
|
|
"ssi.5", "ssi.4", "ssi.3", "ssi.2",
|
|
"ssi.1", "ssi.0",
|
|
"src.9", "src.8", "src.7", "src.6",
|
|
"src.5", "src.4", "src.3", "src.2",
|
|
"src.1", "src.0",
|
|
"dvc.0", "dvc.1",
|
|
"clk_a", "clk_b", "clk_c", "clk_i";
|
|
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
|
resets = <&cpg 1005>,
|
|
<&cpg 1006>, <&cpg 1007>,
|
|
<&cpg 1008>, <&cpg 1009>,
|
|
<&cpg 1010>, <&cpg 1011>,
|
|
<&cpg 1012>, <&cpg 1013>,
|
|
<&cpg 1014>, <&cpg 1015>;
|
|
reset-names = "ssi-all",
|
|
"ssi.9", "ssi.8", "ssi.7", "ssi.6",
|
|
"ssi.5", "ssi.4", "ssi.3", "ssi.2",
|
|
"ssi.1", "ssi.0";
|
|
|
|
status = "disabled";
|
|
|
|
rcar_sound,dvc {
|
|
dvc0: dvc-0 {
|
|
dmas = <&audma1 0xbc>;
|
|
dma-names = "tx";
|
|
};
|
|
dvc1: dvc-1 {
|
|
dmas = <&audma1 0xbe>;
|
|
dma-names = "tx";
|
|
};
|
|
};
|
|
|
|
rcar_sound,src {
|
|
src0: src-0 {
|
|
interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&audma0 0x85>, <&audma1 0x9a>;
|
|
dma-names = "rx", "tx";
|
|
};
|
|
src1: src-1 {
|
|
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&audma0 0x87>, <&audma1 0x9c>;
|
|
dma-names = "rx", "tx";
|
|
};
|
|
src2: src-2 {
|
|
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&audma0 0x89>, <&audma1 0x9e>;
|
|
dma-names = "rx", "tx";
|
|
};
|
|
src3: src-3 {
|
|
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&audma0 0x8b>, <&audma1 0xa0>;
|
|
dma-names = "rx", "tx";
|
|
};
|
|
src4: src-4 {
|
|
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&audma0 0x8d>, <&audma1 0xb0>;
|
|
dma-names = "rx", "tx";
|
|
};
|
|
src5: src-5 {
|
|
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&audma0 0x8f>, <&audma1 0xb2>;
|
|
dma-names = "rx", "tx";
|
|
};
|
|
src6: src-6 {
|
|
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&audma0 0x91>, <&audma1 0xb4>;
|
|
dma-names = "rx", "tx";
|
|
};
|
|
src7: src-7 {
|
|
interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&audma0 0x93>, <&audma1 0xb6>;
|
|
dma-names = "rx", "tx";
|
|
};
|
|
src8: src-8 {
|
|
interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&audma0 0x95>, <&audma1 0xb8>;
|
|
dma-names = "rx", "tx";
|
|
};
|
|
src9: src-9 {
|
|
interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&audma0 0x97>, <&audma1 0xba>;
|
|
dma-names = "rx", "tx";
|
|
};
|
|
};
|
|
|
|
rcar_sound,ssi {
|
|
ssi0: ssi-0 {
|
|
interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&audma0 0x01>, <&audma1 0x02>,
|
|
<&audma0 0x15>, <&audma1 0x16>;
|
|
dma-names = "rx", "tx", "rxu", "txu";
|
|
};
|
|
ssi1: ssi-1 {
|
|
interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&audma0 0x03>, <&audma1 0x04>,
|
|
<&audma0 0x49>, <&audma1 0x4a>;
|
|
dma-names = "rx", "tx", "rxu", "txu";
|
|
};
|
|
ssi2: ssi-2 {
|
|
interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&audma0 0x05>, <&audma1 0x06>,
|
|
<&audma0 0x63>, <&audma1 0x64>;
|
|
dma-names = "rx", "tx", "rxu", "txu";
|
|
};
|
|
ssi3: ssi-3 {
|
|
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&audma0 0x07>, <&audma1 0x08>,
|
|
<&audma0 0x6f>, <&audma1 0x70>;
|
|
dma-names = "rx", "tx", "rxu", "txu";
|
|
};
|
|
ssi4: ssi-4 {
|
|
interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&audma0 0x09>, <&audma1 0x0a>,
|
|
<&audma0 0x71>, <&audma1 0x72>;
|
|
dma-names = "rx", "tx", "rxu", "txu";
|
|
};
|
|
ssi5: ssi-5 {
|
|
interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&audma0 0x0b>, <&audma1 0x0c>,
|
|
<&audma0 0x73>, <&audma1 0x74>;
|
|
dma-names = "rx", "tx", "rxu", "txu";
|
|
};
|
|
ssi6: ssi-6 {
|
|
interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&audma0 0x0d>, <&audma1 0x0e>,
|
|
<&audma0 0x75>, <&audma1 0x76>;
|
|
dma-names = "rx", "tx", "rxu", "txu";
|
|
};
|
|
ssi7: ssi-7 {
|
|
interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&audma0 0x0f>, <&audma1 0x10>,
|
|
<&audma0 0x79>, <&audma1 0x7a>;
|
|
dma-names = "rx", "tx", "rxu", "txu";
|
|
};
|
|
ssi8: ssi-8 {
|
|
interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&audma0 0x11>, <&audma1 0x12>,
|
|
<&audma0 0x7b>, <&audma1 0x7c>;
|
|
dma-names = "rx", "tx", "rxu", "txu";
|
|
};
|
|
ssi9: ssi-9 {
|
|
interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&audma0 0x13>, <&audma1 0x14>,
|
|
<&audma0 0x7d>, <&audma1 0x7e>;
|
|
dma-names = "rx", "tx", "rxu", "txu";
|
|
};
|
|
};
|
|
};
|
|
|
|
audma0: dma-controller@ec700000 {
|
|
compatible = "renesas,dmac-r8a7793",
|
|
"renesas,rcar-dmac";
|
|
reg = <0 0xec700000 0 0x10000>;
|
|
interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "error",
|
|
"ch0", "ch1", "ch2", "ch3",
|
|
"ch4", "ch5", "ch6", "ch7",
|
|
"ch8", "ch9", "ch10", "ch11",
|
|
"ch12";
|
|
clocks = <&cpg CPG_MOD 502>;
|
|
clock-names = "fck";
|
|
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
|
resets = <&cpg 502>;
|
|
#dma-cells = <1>;
|
|
dma-channels = <13>;
|
|
};
|
|
|
|
audma1: dma-controller@ec720000 {
|
|
compatible = "renesas,dmac-r8a7793",
|
|
"renesas,rcar-dmac";
|
|
reg = <0 0xec720000 0 0x10000>;
|
|
interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "error",
|
|
"ch0", "ch1", "ch2", "ch3",
|
|
"ch4", "ch5", "ch6", "ch7",
|
|
"ch8", "ch9", "ch10", "ch11",
|
|
"ch12";
|
|
clocks = <&cpg CPG_MOD 501>;
|
|
clock-names = "fck";
|
|
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
|
resets = <&cpg 501>;
|
|
#dma-cells = <1>;
|
|
dma-channels = <13>;
|
|
};
|
|
|
|
sdhi0: sd@ee100000 {
|
|
compatible = "renesas,sdhi-r8a7793",
|
|
"renesas,rcar-gen2-sdhi";
|
|
reg = <0 0xee100000 0 0x328>;
|
|
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 314>;
|
|
dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
|
|
<&dmac1 0xcd>, <&dmac1 0xce>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
max-frequency = <195000000>;
|
|
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
|
resets = <&cpg 314>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sdhi1: sd@ee140000 {
|
|
compatible = "renesas,sdhi-r8a7793",
|
|
"renesas,rcar-gen2-sdhi";
|
|
reg = <0 0xee140000 0 0x100>;
|
|
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 312>;
|
|
dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
|
|
<&dmac1 0xc1>, <&dmac1 0xc2>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
max-frequency = <97500000>;
|
|
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
|
resets = <&cpg 312>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sdhi2: sd@ee160000 {
|
|
compatible = "renesas,sdhi-r8a7793",
|
|
"renesas,rcar-gen2-sdhi";
|
|
reg = <0 0xee160000 0 0x100>;
|
|
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 311>;
|
|
dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
|
|
<&dmac1 0xd3>, <&dmac1 0xd4>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
max-frequency = <97500000>;
|
|
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
|
resets = <&cpg 311>;
|
|
status = "disabled";
|
|
};
|
|
|
|
mmcif0: mmc@ee200000 {
|
|
compatible = "renesas,mmcif-r8a7793",
|
|
"renesas,sh-mmcif";
|
|
reg = <0 0xee200000 0 0x80>;
|
|
interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 315>;
|
|
dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
|
|
<&dmac1 0xd1>, <&dmac1 0xd2>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
|
resets = <&cpg 315>;
|
|
reg-io-width = <4>;
|
|
status = "disabled";
|
|
max-frequency = <97500000>;
|
|
};
|
|
|
|
ether: ethernet@ee700000 {
|
|
compatible = "renesas,ether-r8a7793",
|
|
"renesas,rcar-gen2-ether";
|
|
reg = <0 0xee700000 0 0x400>;
|
|
interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 813>;
|
|
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
|
resets = <&cpg 813>;
|
|
phy-mode = "rmii";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
gic: interrupt-controller@f1001000 {
|
|
compatible = "arm,gic-400";
|
|
#interrupt-cells = <3>;
|
|
#address-cells = <0>;
|
|
interrupt-controller;
|
|
reg = <0 0xf1001000 0 0x1000>,
|
|
<0 0xf1002000 0 0x2000>,
|
|
<0 0xf1004000 0 0x2000>,
|
|
<0 0xf1006000 0 0x2000>;
|
|
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
|
|
clocks = <&cpg CPG_MOD 408>;
|
|
clock-names = "clk";
|
|
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
|
resets = <&cpg 408>;
|
|
};
|
|
|
|
fdp1@fe940000 {
|
|
compatible = "renesas,fdp1";
|
|
reg = <0 0xfe940000 0 0x2400>;
|
|
interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 119>;
|
|
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
|
resets = <&cpg 119>;
|
|
};
|
|
|
|
fdp1@fe944000 {
|
|
compatible = "renesas,fdp1";
|
|
reg = <0 0xfe944000 0 0x2400>;
|
|
interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 118>;
|
|
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
|
resets = <&cpg 118>;
|
|
};
|
|
|
|
du: display@feb00000 {
|
|
compatible = "renesas,du-r8a7793";
|
|
reg = <0 0xfeb00000 0 0x40000>;
|
|
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 724>,
|
|
<&cpg CPG_MOD 723>;
|
|
clock-names = "du.0", "du.1";
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
du_out_rgb: endpoint {
|
|
};
|
|
};
|
|
port@1 {
|
|
reg = <1>;
|
|
du_out_lvds0: endpoint {
|
|
remote-endpoint = <&lvds0_in>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
lvds0: lvds@feb90000 {
|
|
compatible = "renesas,r8a7793-lvds";
|
|
reg = <0 0xfeb90000 0 0x1c>;
|
|
clocks = <&cpg CPG_MOD 726>;
|
|
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
|
resets = <&cpg 726>;
|
|
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
lvds0_in: endpoint {
|
|
remote-endpoint = <&du_out_lvds0>;
|
|
};
|
|
};
|
|
port@1 {
|
|
reg = <1>;
|
|
lvds0_out: endpoint {
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
prr: chipid@ff000044 {
|
|
compatible = "renesas,prr";
|
|
reg = <0 0xff000044 0 4>;
|
|
};
|
|
|
|
cmt0: timer@ffca0000 {
|
|
compatible = "renesas,r8a7793-cmt0",
|
|
"renesas,rcar-gen2-cmt0";
|
|
reg = <0 0xffca0000 0 0x1004>;
|
|
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 124>;
|
|
clock-names = "fck";
|
|
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
|
resets = <&cpg 124>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
cmt1: timer@e6130000 {
|
|
compatible = "renesas,r8a7793-cmt1",
|
|
"renesas,rcar-gen2-cmt1";
|
|
reg = <0 0xe6130000 0 0x1004>;
|
|
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 329>;
|
|
clock-names = "fck";
|
|
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
|
resets = <&cpg 329>;
|
|
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
thermal-zones {
|
|
cpu_thermal: cpu-thermal {
|
|
polling-delay-passive = <0>;
|
|
polling-delay = <0>;
|
|
|
|
thermal-sensors = <&thermal>;
|
|
|
|
trips {
|
|
cpu-crit {
|
|
temperature = <95000>;
|
|
hysteresis = <0>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
cooling-maps {
|
|
};
|
|
};
|
|
};
|
|
|
|
timer {
|
|
compatible = "arm,armv7-timer";
|
|
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
|
|
};
|
|
|
|
/* External USB clock - can be overridden by the board */
|
|
usb_extal_clk: usb_extal {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <48000000>;
|
|
};
|
|
};
|