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0fa1f0609a
The orion watchdog is expecting to be passed the physcial address of the hardware, and will ioremap() it to give a virtual address it will use as the base address for the hardware. However, when creating the platform resource record, a virtual address was being used. Add the necassary #define's so we can pass the physical address as expected. Tested on Kirkwood and Orion5x. Cc: stable <stable@vger.kernel.org> Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Olof Johansson <olof@lixom.net>
40 lines
1.0 KiB
C
40 lines
1.0 KiB
C
/*
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* arch/arm/mach-orion5x/include/mach/bridge-regs.h
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*
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* Orion CPU Bridge Registers
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef __ASM_ARCH_BRIDGE_REGS_H
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#define __ASM_ARCH_BRIDGE_REGS_H
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#include <mach/orion5x.h>
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#define CPU_CONF (ORION5X_BRIDGE_VIRT_BASE | 0x100)
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#define CPU_CTRL (ORION5X_BRIDGE_VIRT_BASE | 0x104)
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#define RSTOUTn_MASK (ORION5X_BRIDGE_VIRT_BASE | 0x108)
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#define WDT_RESET_OUT_EN 0x0002
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#define CPU_SOFT_RESET (ORION5X_BRIDGE_VIRT_BASE | 0x10c)
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#define BRIDGE_CAUSE (ORION5X_BRIDGE_VIRT_BASE | 0x110)
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#define POWER_MNG_CTRL_REG (ORION5X_BRIDGE_VIRT_BASE | 0x11C)
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#define WDT_INT_REQ 0x0008
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#define BRIDGE_INT_TIMER1_CLR (~0x0004)
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#define MAIN_IRQ_CAUSE (ORION5X_BRIDGE_VIRT_BASE | 0x200)
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#define MAIN_IRQ_MASK (ORION5X_BRIDGE_VIRT_BASE | 0x204)
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#define TIMER_VIRT_BASE (ORION5X_BRIDGE_VIRT_BASE | 0x300)
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#define TIMER_PHYS_BASE (ORION5X_BRIDGE_PHYS_BASE | 0x300)
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#endif
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