Chris Wilson 7fa28e1469 drm/i915: Write GPU relocs harder with gen3 ... Under moderate amounts of GPU stress, we can observe on Bearlake and Pineview (later gen3 models) that we execute the following batch buffer before the write into the batch is coherent. Adding extra (tested with upto 32x) MI_FLUSH to either the invalidation, flush or both phases does not solve the incoherency issue with the relocations, but emitting the MI_STORE_DWORD_IMM twice does. So be it. Fixes: 7dd4f6729f ("drm/i915: Async GPU relocation processing") Testcase: igt/gem_tiled_fence_blits # blb/pnv Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181119154153.15327-1-chris@chris-wilson.co.uk		2018-11-20 09:50:21 +00:00
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drm	drm/i915: Write GPU relocs harder with gen3	2018-11-20 09:50:21 +00:00
host1x	gpu: host1x: Detach Host1x from IOMMU DMA domain on arm32	2018-09-26 17:11:14 +02:00
ipu-v3	drm pull for 4.19-rc1	2018-08-15 17:39:07 -07:00
vga	ALSA: hda - Enable runtime PM only for discrete GPU	2018-09-13 17:58:30 +02:00
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