mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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665ccfa090
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
383 lines
11 KiB
C
383 lines
11 KiB
C
/*
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* R8A7740 processor support
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*
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* Copyright (C) 2011 Renesas Solutions Corp.
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* Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/io.h>
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#include <linux/sh_clk.h>
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#include <linux/clkdev.h>
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#include <mach/common.h>
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#include <mach/r8a7740.h>
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/*
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* | MDx | XTAL1/EXTAL1 | System | EXTALR |
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* Clock |-------+-----------------+ clock | 32.768 | RCLK
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* Mode | 2/1/0 | src MHz | source | KHz | source
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* -------+-------+-----------------+-----------+--------+----------
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* 0 | 0 0 0 | External 20~50 | XTAL1 | O | EXTALR
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* 1 | 0 0 1 | Crystal 20~30 | XTAL1 | O | EXTALR
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* 2 | 0 1 0 | External 40~50 | XTAL1 / 2 | O | EXTALR
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* 3 | 0 1 1 | Crystal 40~50 | XTAL1 / 2 | O | EXTALR
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* 4 | 1 0 0 | External 20~50 | XTAL1 | x | XTAL1 / 1024
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* 5 | 1 0 1 | Crystal 20~30 | XTAL1 | x | XTAL1 / 1024
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* 6 | 1 1 0 | External 40~50 | XTAL1 / 2 | x | XTAL1 / 2048
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* 7 | 1 1 1 | Crystal 40~50 | XTAL1 / 2 | x | XTAL1 / 2048
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*/
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/* CPG registers */
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#define FRQCRA 0xe6150000
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#define FRQCRB 0xe6150004
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#define FRQCRC 0xe61500e0
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#define PLLC01CR 0xe6150028
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#define SUBCKCR 0xe6150080
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#define MSTPSR0 0xe6150030
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#define MSTPSR1 0xe6150038
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#define MSTPSR2 0xe6150040
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#define MSTPSR3 0xe6150048
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#define MSTPSR4 0xe615004c
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#define SMSTPCR0 0xe6150130
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#define SMSTPCR1 0xe6150134
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#define SMSTPCR2 0xe6150138
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#define SMSTPCR3 0xe615013c
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#define SMSTPCR4 0xe6150140
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/* Fixed 32 KHz root clock from EXTALR pin */
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static struct clk extalr_clk = {
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.rate = 32768,
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};
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/*
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* 25MHz default rate for the EXTAL1 root input clock.
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* If needed, reset this with clk_set_rate() from the platform code.
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*/
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static struct clk extal1_clk = {
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.rate = 25000000,
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};
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/*
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* 48MHz default rate for the EXTAL2 root input clock.
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* If needed, reset this with clk_set_rate() from the platform code.
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*/
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static struct clk extal2_clk = {
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.rate = 48000000,
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};
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/*
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* 27MHz default rate for the DV_CLKI root input clock.
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* If needed, reset this with clk_set_rate() from the platform code.
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*/
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static struct clk dv_clk = {
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.rate = 27000000,
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};
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static unsigned long div_recalc(struct clk *clk)
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{
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return clk->parent->rate / (int)(clk->priv);
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}
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static struct clk_ops div_clk_ops = {
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.recalc = div_recalc,
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};
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/* extal1 / 2 */
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static struct clk extal1_div2_clk = {
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.ops = &div_clk_ops,
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.priv = (void *)2,
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.parent = &extal1_clk,
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};
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/* extal1 / 1024 */
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static struct clk extal1_div1024_clk = {
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.ops = &div_clk_ops,
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.priv = (void *)1024,
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.parent = &extal1_clk,
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};
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/* extal1 / 2 / 1024 */
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static struct clk extal1_div2048_clk = {
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.ops = &div_clk_ops,
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.priv = (void *)1024,
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.parent = &extal1_div2_clk,
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};
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/* extal2 / 2 */
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static struct clk extal2_div2_clk = {
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.ops = &div_clk_ops,
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.priv = (void *)2,
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.parent = &extal2_clk,
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};
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static struct clk_ops followparent_clk_ops = {
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.recalc = followparent_recalc,
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};
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/* Main clock */
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static struct clk system_clk = {
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.ops = &followparent_clk_ops,
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};
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static struct clk system_div2_clk = {
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.ops = &div_clk_ops,
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.priv = (void *)2,
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.parent = &system_clk,
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};
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/* r_clk */
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static struct clk r_clk = {
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.ops = &followparent_clk_ops,
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};
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/* PLLC0/PLLC1 */
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static unsigned long pllc01_recalc(struct clk *clk)
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{
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unsigned long mult = 1;
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if (__raw_readl(PLLC01CR) & (1 << 14))
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mult = ((__raw_readl(clk->enable_reg) >> 24) & 0x7f) + 1;
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return clk->parent->rate * mult;
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}
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static struct clk_ops pllc01_clk_ops = {
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.recalc = pllc01_recalc,
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};
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static struct clk pllc0_clk = {
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.ops = &pllc01_clk_ops,
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.flags = CLK_ENABLE_ON_INIT,
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.parent = &system_clk,
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.enable_reg = (void __iomem *)FRQCRC,
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};
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static struct clk pllc1_clk = {
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.ops = &pllc01_clk_ops,
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.flags = CLK_ENABLE_ON_INIT,
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.parent = &system_div2_clk,
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.enable_reg = (void __iomem *)FRQCRA,
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};
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/* PLLC1 / 2 */
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static struct clk pllc1_div2_clk = {
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.ops = &div_clk_ops,
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.priv = (void *)2,
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.parent = &pllc1_clk,
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};
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struct clk *main_clks[] = {
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&extalr_clk,
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&extal1_clk,
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&extal2_clk,
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&extal1_div2_clk,
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&extal1_div1024_clk,
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&extal1_div2048_clk,
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&extal2_div2_clk,
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&dv_clk,
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&system_clk,
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&system_div2_clk,
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&r_clk,
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&pllc0_clk,
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&pllc1_clk,
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&pllc1_div2_clk,
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};
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static void div4_kick(struct clk *clk)
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{
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unsigned long value;
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/* set KICK bit in FRQCRB to update hardware setting */
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value = __raw_readl(FRQCRB);
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value |= (1 << 31);
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__raw_writel(value, FRQCRB);
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}
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static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18,
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24, 32, 36, 48, 0, 72, 96, 0 };
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static struct clk_div_mult_table div4_div_mult_table = {
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.divisors = divisors,
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.nr_divisors = ARRAY_SIZE(divisors),
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};
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static struct clk_div4_table div4_table = {
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.div_mult_table = &div4_div_mult_table,
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.kick = div4_kick,
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};
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enum {
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DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_HP,
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DIV4_HPP, DIV4_S, DIV4_ZB, DIV4_M3, DIV4_CP,
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DIV4_NR
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};
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struct clk div4_clks[DIV4_NR] = {
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[DIV4_I] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 20, 0x6fff, CLK_ENABLE_ON_INIT),
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[DIV4_ZG] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 16, 0x6fff, CLK_ENABLE_ON_INIT),
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[DIV4_B] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 8, 0x6fff, CLK_ENABLE_ON_INIT),
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[DIV4_M1] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 4, 0x6fff, CLK_ENABLE_ON_INIT),
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[DIV4_HP] = SH_CLK_DIV4(&pllc1_clk, FRQCRB, 4, 0x6fff, 0),
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[DIV4_HPP] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 20, 0x6fff, 0),
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[DIV4_S] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 12, 0x6fff, 0),
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[DIV4_ZB] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 8, 0x6fff, 0),
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[DIV4_M3] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 4, 0x6fff, 0),
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[DIV4_CP] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 0, 0x6fff, 0),
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};
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enum {
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DIV6_SUB,
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DIV6_NR
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};
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static struct clk div6_clks[DIV6_NR] = {
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[DIV6_SUB] = SH_CLK_DIV6(&pllc1_div2_clk, SUBCKCR, 0),
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};
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enum {
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MSTP125,
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MSTP116, MSTP111, MSTP100, MSTP117,
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MSTP230,
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MSTP222,
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MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
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MSTP329, MSTP323,
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MSTP_NR
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};
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static struct clk mstp_clks[MSTP_NR] = {
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[MSTP125] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR1, 25, 0), /* TMU0 */
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[MSTP117] = SH_CLK_MSTP32(&div4_clks[DIV4_B], SMSTPCR1, 17, 0), /* LCDC1 */
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[MSTP116] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR1, 16, 0), /* IIC0 */
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[MSTP111] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR1, 11, 0), /* TMU1 */
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[MSTP100] = SH_CLK_MSTP32(&div4_clks[DIV4_B], SMSTPCR1, 0, 0), /* LCDC0 */
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[MSTP230] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 30, 0), /* SCIFA6 */
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[MSTP222] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 22, 0), /* SCIFA7 */
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[MSTP207] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 7, 0), /* SCIFA5 */
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[MSTP206] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 6, 0), /* SCIFB */
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[MSTP204] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 4, 0), /* SCIFA0 */
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[MSTP203] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 3, 0), /* SCIFA1 */
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[MSTP202] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 2, 0), /* SCIFA2 */
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[MSTP201] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 1, 0), /* SCIFA3 */
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[MSTP200] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 0, 0), /* SCIFA4 */
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[MSTP329] = SH_CLK_MSTP32(&r_clk, SMSTPCR3, 29, 0), /* CMT10 */
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[MSTP323] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR3, 23, 0), /* IIC1 */
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};
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static struct clk_lookup lookups[] = {
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/* main clocks */
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CLKDEV_CON_ID("extalr", &extalr_clk),
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CLKDEV_CON_ID("extal1", &extal1_clk),
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CLKDEV_CON_ID("extal2", &extal2_clk),
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CLKDEV_CON_ID("extal1_div2", &extal1_div2_clk),
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CLKDEV_CON_ID("extal1_div1024", &extal1_div1024_clk),
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CLKDEV_CON_ID("extal1_div2048", &extal1_div2048_clk),
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CLKDEV_CON_ID("extal2_div2", &extal2_div2_clk),
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CLKDEV_CON_ID("dv_clk", &dv_clk),
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CLKDEV_CON_ID("system_clk", &system_clk),
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CLKDEV_CON_ID("system_div2_clk", &system_div2_clk),
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CLKDEV_CON_ID("r_clk", &r_clk),
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CLKDEV_CON_ID("pllc0_clk", &pllc0_clk),
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CLKDEV_CON_ID("pllc1_clk", &pllc1_clk),
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CLKDEV_CON_ID("pllc1_div2_clk", &pllc1_div2_clk),
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/* DIV4 clocks */
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CLKDEV_CON_ID("i_clk", &div4_clks[DIV4_I]),
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CLKDEV_CON_ID("zg_clk", &div4_clks[DIV4_ZG]),
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CLKDEV_CON_ID("b_clk", &div4_clks[DIV4_B]),
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CLKDEV_CON_ID("m1_clk", &div4_clks[DIV4_M1]),
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CLKDEV_CON_ID("hp_clk", &div4_clks[DIV4_HP]),
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CLKDEV_CON_ID("hpp_clk", &div4_clks[DIV4_HPP]),
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CLKDEV_CON_ID("s_clk", &div4_clks[DIV4_S]),
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CLKDEV_CON_ID("zb_clk", &div4_clks[DIV4_ZB]),
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CLKDEV_CON_ID("m3_clk", &div4_clks[DIV4_M3]),
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CLKDEV_CON_ID("cp_clk", &div4_clks[DIV4_CP]),
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/* DIV6 clocks */
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CLKDEV_CON_ID("sub_clk", &div6_clks[DIV6_SUB]),
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/* MSTP32 clocks */
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CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[MSTP100]),
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CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP111]),
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CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]),
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CLKDEV_DEV_ID("sh_mobile_lcdc_fb.1", &mstp_clks[MSTP117]),
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CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP125]),
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CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]),
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CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP201]),
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CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP202]),
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CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]),
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CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]),
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CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP206]),
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CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]),
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CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP222]),
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CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP230]),
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CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]),
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CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]),
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};
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void __init r8a7740_clock_init(u8 md_ck)
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{
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int k, ret = 0;
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/* detect system clock parent */
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if (md_ck & MD_CK1)
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system_clk.parent = &extal1_div2_clk;
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else
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system_clk.parent = &extal1_clk;
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/* detect RCLK parent */
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switch (md_ck & (MD_CK2 | MD_CK1)) {
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case MD_CK2 | MD_CK1:
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r_clk.parent = &extal1_div2048_clk;
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break;
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case MD_CK2:
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r_clk.parent = &extal1_div1024_clk;
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break;
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case MD_CK1:
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default:
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r_clk.parent = &extalr_clk;
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break;
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}
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for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
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ret = clk_register(main_clks[k]);
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if (!ret)
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ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
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if (!ret)
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ret = sh_clk_div6_register(div6_clks, DIV6_NR);
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if (!ret)
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ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
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clkdev_add_table(lookups, ARRAY_SIZE(lookups));
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if (!ret)
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clk_init();
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else
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panic("failed to setup r8a7740 clocks\n");
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}
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