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0445e7a58e
Commit 8f622422 ("perf events: Add generic front-end and back-end
stalled cycle event definitions") added two new ABI events for counting
stalled cycles.
This patch adds support for these new events to the ARM perf
implementation.
Cc: Jamie Iles <jamie@jamieiles.com>
Cc: Jean Pihet <j-pihet@ti.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
1151 lines
31 KiB
C
1151 lines
31 KiB
C
/*
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* ARMv7 Cortex-A8 and Cortex-A9 Performance Events handling code.
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*
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* ARMv7 support: Jean Pihet <jpihet@mvista.com>
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* 2010 (c) MontaVista Software, LLC.
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*
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* Copied from ARMv6 code, with the low level code inspired
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* by the ARMv7 Oprofile code.
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*
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* Cortex-A8 has up to 4 configurable performance counters and
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* a single cycle counter.
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* Cortex-A9 has up to 31 configurable performance counters and
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* a single cycle counter.
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*
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* All counters can be enabled/disabled and IRQ masked separately. The cycle
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* counter and all 4 performance counters together can be reset separately.
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*/
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#ifdef CONFIG_CPU_V7
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static struct arm_pmu armv7pmu;
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/*
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* Common ARMv7 event types
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*
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* Note: An implementation may not be able to count all of these events
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* but the encodings are considered to be `reserved' in the case that
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* they are not available.
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*/
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enum armv7_perf_types {
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ARMV7_PERFCTR_PMNC_SW_INCR = 0x00,
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ARMV7_PERFCTR_L1_ICACHE_REFILL = 0x01,
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ARMV7_PERFCTR_ITLB_REFILL = 0x02,
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ARMV7_PERFCTR_L1_DCACHE_REFILL = 0x03,
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ARMV7_PERFCTR_L1_DCACHE_ACCESS = 0x04,
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ARMV7_PERFCTR_DTLB_REFILL = 0x05,
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ARMV7_PERFCTR_MEM_READ = 0x06,
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ARMV7_PERFCTR_MEM_WRITE = 0x07,
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ARMV7_PERFCTR_INSTR_EXECUTED = 0x08,
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ARMV7_PERFCTR_EXC_TAKEN = 0x09,
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ARMV7_PERFCTR_EXC_EXECUTED = 0x0A,
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ARMV7_PERFCTR_CID_WRITE = 0x0B,
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/*
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* ARMV7_PERFCTR_PC_WRITE is equivalent to HW_BRANCH_INSTRUCTIONS.
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* It counts:
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* - all (taken) branch instructions,
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* - instructions that explicitly write the PC,
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* - exception generating instructions.
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*/
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ARMV7_PERFCTR_PC_WRITE = 0x0C,
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ARMV7_PERFCTR_PC_IMM_BRANCH = 0x0D,
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ARMV7_PERFCTR_PC_PROC_RETURN = 0x0E,
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ARMV7_PERFCTR_MEM_UNALIGNED_ACCESS = 0x0F,
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ARMV7_PERFCTR_PC_BRANCH_MIS_PRED = 0x10,
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ARMV7_PERFCTR_CLOCK_CYCLES = 0x11,
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ARMV7_PERFCTR_PC_BRANCH_PRED = 0x12,
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/* These events are defined by the PMUv2 supplement (ARM DDI 0457A). */
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ARMV7_PERFCTR_MEM_ACCESS = 0x13,
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ARMV7_PERFCTR_L1_ICACHE_ACCESS = 0x14,
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ARMV7_PERFCTR_L1_DCACHE_WB = 0x15,
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ARMV7_PERFCTR_L2_CACHE_ACCESS = 0x16,
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ARMV7_PERFCTR_L2_CACHE_REFILL = 0x17,
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ARMV7_PERFCTR_L2_CACHE_WB = 0x18,
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ARMV7_PERFCTR_BUS_ACCESS = 0x19,
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ARMV7_PERFCTR_MEM_ERROR = 0x1A,
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ARMV7_PERFCTR_INSTR_SPEC = 0x1B,
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ARMV7_PERFCTR_TTBR_WRITE = 0x1C,
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ARMV7_PERFCTR_BUS_CYCLES = 0x1D,
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ARMV7_PERFCTR_CPU_CYCLES = 0xFF
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};
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/* ARMv7 Cortex-A8 specific event types */
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enum armv7_a8_perf_types {
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ARMV7_A8_PERFCTR_L2_CACHE_ACCESS = 0x43,
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ARMV7_A8_PERFCTR_L2_CACHE_REFILL = 0x44,
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ARMV7_A8_PERFCTR_L1_ICACHE_ACCESS = 0x50,
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ARMV7_A8_PERFCTR_STALL_ISIDE = 0x56,
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};
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/* ARMv7 Cortex-A9 specific event types */
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enum armv7_a9_perf_types {
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ARMV7_A9_PERFCTR_INSTR_CORE_RENAME = 0x68,
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ARMV7_A9_PERFCTR_STALL_ICACHE = 0x60,
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ARMV7_A9_PERFCTR_STALL_DISPATCH = 0x66,
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};
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/* ARMv7 Cortex-A5 specific event types */
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enum armv7_a5_perf_types {
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ARMV7_A5_PERFCTR_PREFETCH_LINEFILL = 0xc2,
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ARMV7_A5_PERFCTR_PREFETCH_LINEFILL_DROP = 0xc3,
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};
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/* ARMv7 Cortex-A15 specific event types */
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enum armv7_a15_perf_types {
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ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_READ = 0x40,
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ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_WRITE = 0x41,
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ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_READ = 0x42,
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ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_WRITE = 0x43,
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ARMV7_A15_PERFCTR_DTLB_REFILL_L1_READ = 0x4C,
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ARMV7_A15_PERFCTR_DTLB_REFILL_L1_WRITE = 0x4D,
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ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_READ = 0x50,
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ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_WRITE = 0x51,
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ARMV7_A15_PERFCTR_L2_CACHE_REFILL_READ = 0x52,
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ARMV7_A15_PERFCTR_L2_CACHE_REFILL_WRITE = 0x53,
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ARMV7_A15_PERFCTR_PC_WRITE_SPEC = 0x76,
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};
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/*
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* Cortex-A8 HW events mapping
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*
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* The hardware events that we support. We do support cache operations but
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* we have harvard caches and no way to combine instruction and data
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* accesses/misses in hardware.
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*/
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static const unsigned armv7_a8_perf_map[PERF_COUNT_HW_MAX] = {
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[PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES,
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[PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED,
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[PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
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[PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
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[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE,
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[PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
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[PERF_COUNT_HW_BUS_CYCLES] = HW_OP_UNSUPPORTED,
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[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV7_A8_PERFCTR_STALL_ISIDE,
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[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = HW_OP_UNSUPPORTED,
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};
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static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
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[PERF_COUNT_HW_CACHE_OP_MAX]
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[PERF_COUNT_HW_CACHE_RESULT_MAX] = {
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[C(L1D)] = {
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/*
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* The performance counters don't differentiate between read
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* and write accesses/misses so this isn't strictly correct,
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* but it's the best we can do. Writes and reads get
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* combined.
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*/
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
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[C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
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},
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
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[C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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},
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[C(L1I)] = {
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = ARMV7_A8_PERFCTR_L1_ICACHE_ACCESS,
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[C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
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},
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] = ARMV7_A8_PERFCTR_L1_ICACHE_ACCESS,
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[C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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},
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[C(LL)] = {
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = ARMV7_A8_PERFCTR_L2_CACHE_ACCESS,
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[C(RESULT_MISS)] = ARMV7_A8_PERFCTR_L2_CACHE_REFILL,
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},
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] = ARMV7_A8_PERFCTR_L2_CACHE_ACCESS,
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[C(RESULT_MISS)] = ARMV7_A8_PERFCTR_L2_CACHE_REFILL,
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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},
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[C(DTLB)] = {
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
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},
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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},
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[C(ITLB)] = {
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
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},
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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},
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[C(BPU)] = {
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
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[C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
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},
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
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[C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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},
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[C(NODE)] = {
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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},
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};
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/*
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* Cortex-A9 HW events mapping
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*/
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static const unsigned armv7_a9_perf_map[PERF_COUNT_HW_MAX] = {
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[PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES,
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[PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_A9_PERFCTR_INSTR_CORE_RENAME,
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[PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
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[PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
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[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE,
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[PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
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[PERF_COUNT_HW_BUS_CYCLES] = HW_OP_UNSUPPORTED,
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[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV7_A9_PERFCTR_STALL_ICACHE,
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[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = ARMV7_A9_PERFCTR_STALL_DISPATCH,
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};
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static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
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[PERF_COUNT_HW_CACHE_OP_MAX]
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[PERF_COUNT_HW_CACHE_RESULT_MAX] = {
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[C(L1D)] = {
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/*
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* The performance counters don't differentiate between read
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* and write accesses/misses so this isn't strictly correct,
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* but it's the best we can do. Writes and reads get
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* combined.
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*/
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
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[C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
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},
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
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[C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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},
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[C(L1I)] = {
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
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},
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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},
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[C(LL)] = {
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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},
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[C(DTLB)] = {
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
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},
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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},
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[C(ITLB)] = {
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
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},
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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},
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[C(BPU)] = {
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
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[C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
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},
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
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[C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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},
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[C(NODE)] = {
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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},
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};
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/*
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* Cortex-A5 HW events mapping
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*/
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static const unsigned armv7_a5_perf_map[PERF_COUNT_HW_MAX] = {
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[PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES,
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[PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED,
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[PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
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[PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
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[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE,
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[PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
|
|
[PERF_COUNT_HW_BUS_CYCLES] = HW_OP_UNSUPPORTED,
|
|
[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = HW_OP_UNSUPPORTED,
|
|
[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = HW_OP_UNSUPPORTED,
|
|
};
|
|
|
|
static const unsigned armv7_a5_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
|
|
[PERF_COUNT_HW_CACHE_OP_MAX]
|
|
[PERF_COUNT_HW_CACHE_RESULT_MAX] = {
|
|
[C(L1D)] = {
|
|
[C(OP_READ)] = {
|
|
[C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
|
|
[C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
|
|
},
|
|
[C(OP_WRITE)] = {
|
|
[C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
|
|
[C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
|
|
},
|
|
[C(OP_PREFETCH)] = {
|
|
[C(RESULT_ACCESS)] = ARMV7_A5_PERFCTR_PREFETCH_LINEFILL,
|
|
[C(RESULT_MISS)] = ARMV7_A5_PERFCTR_PREFETCH_LINEFILL_DROP,
|
|
},
|
|
},
|
|
[C(L1I)] = {
|
|
[C(OP_READ)] = {
|
|
[C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS,
|
|
[C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
|
|
},
|
|
[C(OP_WRITE)] = {
|
|
[C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS,
|
|
[C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
|
|
},
|
|
/*
|
|
* The prefetch counters don't differentiate between the I
|
|
* side and the D side.
|
|
*/
|
|
[C(OP_PREFETCH)] = {
|
|
[C(RESULT_ACCESS)] = ARMV7_A5_PERFCTR_PREFETCH_LINEFILL,
|
|
[C(RESULT_MISS)] = ARMV7_A5_PERFCTR_PREFETCH_LINEFILL_DROP,
|
|
},
|
|
},
|
|
[C(LL)] = {
|
|
[C(OP_READ)] = {
|
|
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
|
|
[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
|
|
},
|
|
[C(OP_WRITE)] = {
|
|
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
|
|
[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
|
|
},
|
|
[C(OP_PREFETCH)] = {
|
|
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
|
|
[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
|
|
},
|
|
},
|
|
[C(DTLB)] = {
|
|
[C(OP_READ)] = {
|
|
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
|
|
[C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
|
|
},
|
|
[C(OP_WRITE)] = {
|
|
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
|
|
[C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
|
|
},
|
|
[C(OP_PREFETCH)] = {
|
|
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
|
|
[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
|
|
},
|
|
},
|
|
[C(ITLB)] = {
|
|
[C(OP_READ)] = {
|
|
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
|
|
[C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
|
|
},
|
|
[C(OP_WRITE)] = {
|
|
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
|
|
[C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
|
|
},
|
|
[C(OP_PREFETCH)] = {
|
|
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
|
|
[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
|
|
},
|
|
},
|
|
[C(BPU)] = {
|
|
[C(OP_READ)] = {
|
|
[C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
|
|
[C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
|
|
},
|
|
[C(OP_WRITE)] = {
|
|
[C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
|
|
[C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
|
|
},
|
|
[C(OP_PREFETCH)] = {
|
|
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
|
|
[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
|
|
},
|
|
},
|
|
};
|
|
|
|
/*
|
|
* Cortex-A15 HW events mapping
|
|
*/
|
|
static const unsigned armv7_a15_perf_map[PERF_COUNT_HW_MAX] = {
|
|
[PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES,
|
|
[PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED,
|
|
[PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
|
|
[PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
|
|
[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_A15_PERFCTR_PC_WRITE_SPEC,
|
|
[PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
|
|
[PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_BUS_CYCLES,
|
|
[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = HW_OP_UNSUPPORTED,
|
|
[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = HW_OP_UNSUPPORTED,
|
|
};
|
|
|
|
static const unsigned armv7_a15_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
|
|
[PERF_COUNT_HW_CACHE_OP_MAX]
|
|
[PERF_COUNT_HW_CACHE_RESULT_MAX] = {
|
|
[C(L1D)] = {
|
|
[C(OP_READ)] = {
|
|
[C(RESULT_ACCESS)] = ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_READ,
|
|
[C(RESULT_MISS)] = ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_READ,
|
|
},
|
|
[C(OP_WRITE)] = {
|
|
[C(RESULT_ACCESS)] = ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_WRITE,
|
|
[C(RESULT_MISS)] = ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_WRITE,
|
|
},
|
|
[C(OP_PREFETCH)] = {
|
|
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
|
|
[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
|
|
},
|
|
},
|
|
[C(L1I)] = {
|
|
/*
|
|
* Not all performance counters differentiate between read
|
|
* and write accesses/misses so we're not always strictly
|
|
* correct, but it's the best we can do. Writes and reads get
|
|
* combined in these cases.
|
|
*/
|
|
[C(OP_READ)] = {
|
|
[C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS,
|
|
[C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
|
|
},
|
|
[C(OP_WRITE)] = {
|
|
[C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS,
|
|
[C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
|
|
},
|
|
[C(OP_PREFETCH)] = {
|
|
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
|
|
[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
|
|
},
|
|
},
|
|
[C(LL)] = {
|
|
[C(OP_READ)] = {
|
|
[C(RESULT_ACCESS)] = ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_READ,
|
|
[C(RESULT_MISS)] = ARMV7_A15_PERFCTR_L2_CACHE_REFILL_READ,
|
|
},
|
|
[C(OP_WRITE)] = {
|
|
[C(RESULT_ACCESS)] = ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_WRITE,
|
|
[C(RESULT_MISS)] = ARMV7_A15_PERFCTR_L2_CACHE_REFILL_WRITE,
|
|
},
|
|
[C(OP_PREFETCH)] = {
|
|
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
|
|
[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
|
|
},
|
|
},
|
|
[C(DTLB)] = {
|
|
[C(OP_READ)] = {
|
|
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
|
|
[C(RESULT_MISS)] = ARMV7_A15_PERFCTR_DTLB_REFILL_L1_READ,
|
|
},
|
|
[C(OP_WRITE)] = {
|
|
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
|
|
[C(RESULT_MISS)] = ARMV7_A15_PERFCTR_DTLB_REFILL_L1_WRITE,
|
|
},
|
|
[C(OP_PREFETCH)] = {
|
|
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
|
|
[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
|
|
},
|
|
},
|
|
[C(ITLB)] = {
|
|
[C(OP_READ)] = {
|
|
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
|
|
[C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
|
|
},
|
|
[C(OP_WRITE)] = {
|
|
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
|
|
[C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
|
|
},
|
|
[C(OP_PREFETCH)] = {
|
|
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
|
|
[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
|
|
},
|
|
},
|
|
[C(BPU)] = {
|
|
[C(OP_READ)] = {
|
|
[C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
|
|
[C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
|
|
},
|
|
[C(OP_WRITE)] = {
|
|
[C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
|
|
[C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
|
|
},
|
|
[C(OP_PREFETCH)] = {
|
|
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
|
|
[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
|
|
},
|
|
},
|
|
};
|
|
|
|
/*
|
|
* Perf Events' indices
|
|
*/
|
|
#define ARMV7_IDX_CYCLE_COUNTER 0
|
|
#define ARMV7_IDX_COUNTER0 1
|
|
#define ARMV7_IDX_COUNTER_LAST (ARMV7_IDX_CYCLE_COUNTER + cpu_pmu->num_events - 1)
|
|
|
|
#define ARMV7_MAX_COUNTERS 32
|
|
#define ARMV7_COUNTER_MASK (ARMV7_MAX_COUNTERS - 1)
|
|
|
|
/*
|
|
* ARMv7 low level PMNC access
|
|
*/
|
|
|
|
/*
|
|
* Perf Event to low level counters mapping
|
|
*/
|
|
#define ARMV7_IDX_TO_COUNTER(x) \
|
|
(((x) - ARMV7_IDX_COUNTER0) & ARMV7_COUNTER_MASK)
|
|
|
|
/*
|
|
* Per-CPU PMNC: config reg
|
|
*/
|
|
#define ARMV7_PMNC_E (1 << 0) /* Enable all counters */
|
|
#define ARMV7_PMNC_P (1 << 1) /* Reset all counters */
|
|
#define ARMV7_PMNC_C (1 << 2) /* Cycle counter reset */
|
|
#define ARMV7_PMNC_D (1 << 3) /* CCNT counts every 64th cpu cycle */
|
|
#define ARMV7_PMNC_X (1 << 4) /* Export to ETM */
|
|
#define ARMV7_PMNC_DP (1 << 5) /* Disable CCNT if non-invasive debug*/
|
|
#define ARMV7_PMNC_N_SHIFT 11 /* Number of counters supported */
|
|
#define ARMV7_PMNC_N_MASK 0x1f
|
|
#define ARMV7_PMNC_MASK 0x3f /* Mask for writable bits */
|
|
|
|
/*
|
|
* FLAG: counters overflow flag status reg
|
|
*/
|
|
#define ARMV7_FLAG_MASK 0xffffffff /* Mask for writable bits */
|
|
#define ARMV7_OVERFLOWED_MASK ARMV7_FLAG_MASK
|
|
|
|
/*
|
|
* PMXEVTYPER: Event selection reg
|
|
*/
|
|
#define ARMV7_EVTYPE_MASK 0xc00000ff /* Mask for writable bits */
|
|
#define ARMV7_EVTYPE_EVENT 0xff /* Mask for EVENT bits */
|
|
|
|
/*
|
|
* Event filters for PMUv2
|
|
*/
|
|
#define ARMV7_EXCLUDE_PL1 (1 << 31)
|
|
#define ARMV7_EXCLUDE_USER (1 << 30)
|
|
#define ARMV7_INCLUDE_HYP (1 << 27)
|
|
|
|
static inline u32 armv7_pmnc_read(void)
|
|
{
|
|
u32 val;
|
|
asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r"(val));
|
|
return val;
|
|
}
|
|
|
|
static inline void armv7_pmnc_write(u32 val)
|
|
{
|
|
val &= ARMV7_PMNC_MASK;
|
|
isb();
|
|
asm volatile("mcr p15, 0, %0, c9, c12, 0" : : "r"(val));
|
|
}
|
|
|
|
static inline int armv7_pmnc_has_overflowed(u32 pmnc)
|
|
{
|
|
return pmnc & ARMV7_OVERFLOWED_MASK;
|
|
}
|
|
|
|
static inline int armv7_pmnc_counter_valid(int idx)
|
|
{
|
|
return idx >= ARMV7_IDX_CYCLE_COUNTER && idx <= ARMV7_IDX_COUNTER_LAST;
|
|
}
|
|
|
|
static inline int armv7_pmnc_counter_has_overflowed(u32 pmnc, int idx)
|
|
{
|
|
int ret = 0;
|
|
u32 counter;
|
|
|
|
if (!armv7_pmnc_counter_valid(idx)) {
|
|
pr_err("CPU%u checking wrong counter %d overflow status\n",
|
|
smp_processor_id(), idx);
|
|
} else {
|
|
counter = ARMV7_IDX_TO_COUNTER(idx);
|
|
ret = pmnc & BIT(counter);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static inline int armv7_pmnc_select_counter(int idx)
|
|
{
|
|
u32 counter;
|
|
|
|
if (!armv7_pmnc_counter_valid(idx)) {
|
|
pr_err("CPU%u selecting wrong PMNC counter %d\n",
|
|
smp_processor_id(), idx);
|
|
return -EINVAL;
|
|
}
|
|
|
|
counter = ARMV7_IDX_TO_COUNTER(idx);
|
|
asm volatile("mcr p15, 0, %0, c9, c12, 5" : : "r" (counter));
|
|
isb();
|
|
|
|
return idx;
|
|
}
|
|
|
|
static inline u32 armv7pmu_read_counter(int idx)
|
|
{
|
|
u32 value = 0;
|
|
|
|
if (!armv7_pmnc_counter_valid(idx))
|
|
pr_err("CPU%u reading wrong counter %d\n",
|
|
smp_processor_id(), idx);
|
|
else if (idx == ARMV7_IDX_CYCLE_COUNTER)
|
|
asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (value));
|
|
else if (armv7_pmnc_select_counter(idx) == idx)
|
|
asm volatile("mrc p15, 0, %0, c9, c13, 2" : "=r" (value));
|
|
|
|
return value;
|
|
}
|
|
|
|
static inline void armv7pmu_write_counter(int idx, u32 value)
|
|
{
|
|
if (!armv7_pmnc_counter_valid(idx))
|
|
pr_err("CPU%u writing wrong counter %d\n",
|
|
smp_processor_id(), idx);
|
|
else if (idx == ARMV7_IDX_CYCLE_COUNTER)
|
|
asm volatile("mcr p15, 0, %0, c9, c13, 0" : : "r" (value));
|
|
else if (armv7_pmnc_select_counter(idx) == idx)
|
|
asm volatile("mcr p15, 0, %0, c9, c13, 2" : : "r" (value));
|
|
}
|
|
|
|
static inline void armv7_pmnc_write_evtsel(int idx, u32 val)
|
|
{
|
|
if (armv7_pmnc_select_counter(idx) == idx) {
|
|
val &= ARMV7_EVTYPE_MASK;
|
|
asm volatile("mcr p15, 0, %0, c9, c13, 1" : : "r" (val));
|
|
}
|
|
}
|
|
|
|
static inline int armv7_pmnc_enable_counter(int idx)
|
|
{
|
|
u32 counter;
|
|
|
|
if (!armv7_pmnc_counter_valid(idx)) {
|
|
pr_err("CPU%u enabling wrong PMNC counter %d\n",
|
|
smp_processor_id(), idx);
|
|
return -EINVAL;
|
|
}
|
|
|
|
counter = ARMV7_IDX_TO_COUNTER(idx);
|
|
asm volatile("mcr p15, 0, %0, c9, c12, 1" : : "r" (BIT(counter)));
|
|
return idx;
|
|
}
|
|
|
|
static inline int armv7_pmnc_disable_counter(int idx)
|
|
{
|
|
u32 counter;
|
|
|
|
if (!armv7_pmnc_counter_valid(idx)) {
|
|
pr_err("CPU%u disabling wrong PMNC counter %d\n",
|
|
smp_processor_id(), idx);
|
|
return -EINVAL;
|
|
}
|
|
|
|
counter = ARMV7_IDX_TO_COUNTER(idx);
|
|
asm volatile("mcr p15, 0, %0, c9, c12, 2" : : "r" (BIT(counter)));
|
|
return idx;
|
|
}
|
|
|
|
static inline int armv7_pmnc_enable_intens(int idx)
|
|
{
|
|
u32 counter;
|
|
|
|
if (!armv7_pmnc_counter_valid(idx)) {
|
|
pr_err("CPU%u enabling wrong PMNC counter IRQ enable %d\n",
|
|
smp_processor_id(), idx);
|
|
return -EINVAL;
|
|
}
|
|
|
|
counter = ARMV7_IDX_TO_COUNTER(idx);
|
|
asm volatile("mcr p15, 0, %0, c9, c14, 1" : : "r" (BIT(counter)));
|
|
return idx;
|
|
}
|
|
|
|
static inline int armv7_pmnc_disable_intens(int idx)
|
|
{
|
|
u32 counter;
|
|
|
|
if (!armv7_pmnc_counter_valid(idx)) {
|
|
pr_err("CPU%u disabling wrong PMNC counter IRQ enable %d\n",
|
|
smp_processor_id(), idx);
|
|
return -EINVAL;
|
|
}
|
|
|
|
counter = ARMV7_IDX_TO_COUNTER(idx);
|
|
asm volatile("mcr p15, 0, %0, c9, c14, 2" : : "r" (BIT(counter)));
|
|
return idx;
|
|
}
|
|
|
|
static inline u32 armv7_pmnc_getreset_flags(void)
|
|
{
|
|
u32 val;
|
|
|
|
/* Read */
|
|
asm volatile("mrc p15, 0, %0, c9, c12, 3" : "=r" (val));
|
|
|
|
/* Write to clear flags */
|
|
val &= ARMV7_FLAG_MASK;
|
|
asm volatile("mcr p15, 0, %0, c9, c12, 3" : : "r" (val));
|
|
|
|
return val;
|
|
}
|
|
|
|
#ifdef DEBUG
|
|
static void armv7_pmnc_dump_regs(void)
|
|
{
|
|
u32 val;
|
|
unsigned int cnt;
|
|
|
|
printk(KERN_INFO "PMNC registers dump:\n");
|
|
|
|
asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r" (val));
|
|
printk(KERN_INFO "PMNC =0x%08x\n", val);
|
|
|
|
asm volatile("mrc p15, 0, %0, c9, c12, 1" : "=r" (val));
|
|
printk(KERN_INFO "CNTENS=0x%08x\n", val);
|
|
|
|
asm volatile("mrc p15, 0, %0, c9, c14, 1" : "=r" (val));
|
|
printk(KERN_INFO "INTENS=0x%08x\n", val);
|
|
|
|
asm volatile("mrc p15, 0, %0, c9, c12, 3" : "=r" (val));
|
|
printk(KERN_INFO "FLAGS =0x%08x\n", val);
|
|
|
|
asm volatile("mrc p15, 0, %0, c9, c12, 5" : "=r" (val));
|
|
printk(KERN_INFO "SELECT=0x%08x\n", val);
|
|
|
|
asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (val));
|
|
printk(KERN_INFO "CCNT =0x%08x\n", val);
|
|
|
|
for (cnt = ARMV7_IDX_COUNTER0; cnt <= ARMV7_IDX_COUNTER_LAST; cnt++) {
|
|
armv7_pmnc_select_counter(cnt);
|
|
asm volatile("mrc p15, 0, %0, c9, c13, 2" : "=r" (val));
|
|
printk(KERN_INFO "CNT[%d] count =0x%08x\n",
|
|
ARMV7_IDX_TO_COUNTER(cnt), val);
|
|
asm volatile("mrc p15, 0, %0, c9, c13, 1" : "=r" (val));
|
|
printk(KERN_INFO "CNT[%d] evtsel=0x%08x\n",
|
|
ARMV7_IDX_TO_COUNTER(cnt), val);
|
|
}
|
|
}
|
|
#endif
|
|
|
|
static void armv7pmu_enable_event(struct hw_perf_event *hwc, int idx)
|
|
{
|
|
unsigned long flags;
|
|
struct pmu_hw_events *events = cpu_pmu->get_hw_events();
|
|
|
|
/*
|
|
* Enable counter and interrupt, and set the counter to count
|
|
* the event that we're interested in.
|
|
*/
|
|
raw_spin_lock_irqsave(&events->pmu_lock, flags);
|
|
|
|
/*
|
|
* Disable counter
|
|
*/
|
|
armv7_pmnc_disable_counter(idx);
|
|
|
|
/*
|
|
* Set event (if destined for PMNx counters)
|
|
* We only need to set the event for the cycle counter if we
|
|
* have the ability to perform event filtering.
|
|
*/
|
|
if (armv7pmu.set_event_filter || idx != ARMV7_IDX_CYCLE_COUNTER)
|
|
armv7_pmnc_write_evtsel(idx, hwc->config_base);
|
|
|
|
/*
|
|
* Enable interrupt for this counter
|
|
*/
|
|
armv7_pmnc_enable_intens(idx);
|
|
|
|
/*
|
|
* Enable counter
|
|
*/
|
|
armv7_pmnc_enable_counter(idx);
|
|
|
|
raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
|
|
}
|
|
|
|
static void armv7pmu_disable_event(struct hw_perf_event *hwc, int idx)
|
|
{
|
|
unsigned long flags;
|
|
struct pmu_hw_events *events = cpu_pmu->get_hw_events();
|
|
|
|
/*
|
|
* Disable counter and interrupt
|
|
*/
|
|
raw_spin_lock_irqsave(&events->pmu_lock, flags);
|
|
|
|
/*
|
|
* Disable counter
|
|
*/
|
|
armv7_pmnc_disable_counter(idx);
|
|
|
|
/*
|
|
* Disable interrupt for this counter
|
|
*/
|
|
armv7_pmnc_disable_intens(idx);
|
|
|
|
raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
|
|
}
|
|
|
|
static irqreturn_t armv7pmu_handle_irq(int irq_num, void *dev)
|
|
{
|
|
u32 pmnc;
|
|
struct perf_sample_data data;
|
|
struct pmu_hw_events *cpuc;
|
|
struct pt_regs *regs;
|
|
int idx;
|
|
|
|
/*
|
|
* Get and reset the IRQ flags
|
|
*/
|
|
pmnc = armv7_pmnc_getreset_flags();
|
|
|
|
/*
|
|
* Did an overflow occur?
|
|
*/
|
|
if (!armv7_pmnc_has_overflowed(pmnc))
|
|
return IRQ_NONE;
|
|
|
|
/*
|
|
* Handle the counter(s) overflow(s)
|
|
*/
|
|
regs = get_irq_regs();
|
|
|
|
perf_sample_data_init(&data, 0);
|
|
|
|
cpuc = &__get_cpu_var(cpu_hw_events);
|
|
for (idx = 0; idx < cpu_pmu->num_events; ++idx) {
|
|
struct perf_event *event = cpuc->events[idx];
|
|
struct hw_perf_event *hwc;
|
|
|
|
/*
|
|
* We have a single interrupt for all counters. Check that
|
|
* each counter has overflowed before we process it.
|
|
*/
|
|
if (!armv7_pmnc_counter_has_overflowed(pmnc, idx))
|
|
continue;
|
|
|
|
hwc = &event->hw;
|
|
armpmu_event_update(event, hwc, idx, 1);
|
|
data.period = event->hw.last_period;
|
|
if (!armpmu_event_set_period(event, hwc, idx))
|
|
continue;
|
|
|
|
if (perf_event_overflow(event, &data, regs))
|
|
cpu_pmu->disable(hwc, idx);
|
|
}
|
|
|
|
/*
|
|
* Handle the pending perf events.
|
|
*
|
|
* Note: this call *must* be run with interrupts disabled. For
|
|
* platforms that can have the PMU interrupts raised as an NMI, this
|
|
* will not work.
|
|
*/
|
|
irq_work_run();
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static void armv7pmu_start(void)
|
|
{
|
|
unsigned long flags;
|
|
struct pmu_hw_events *events = cpu_pmu->get_hw_events();
|
|
|
|
raw_spin_lock_irqsave(&events->pmu_lock, flags);
|
|
/* Enable all counters */
|
|
armv7_pmnc_write(armv7_pmnc_read() | ARMV7_PMNC_E);
|
|
raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
|
|
}
|
|
|
|
static void armv7pmu_stop(void)
|
|
{
|
|
unsigned long flags;
|
|
struct pmu_hw_events *events = cpu_pmu->get_hw_events();
|
|
|
|
raw_spin_lock_irqsave(&events->pmu_lock, flags);
|
|
/* Disable all counters */
|
|
armv7_pmnc_write(armv7_pmnc_read() & ~ARMV7_PMNC_E);
|
|
raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
|
|
}
|
|
|
|
static int armv7pmu_get_event_idx(struct pmu_hw_events *cpuc,
|
|
struct hw_perf_event *event)
|
|
{
|
|
int idx;
|
|
unsigned long evtype = event->config_base & ARMV7_EVTYPE_EVENT;
|
|
|
|
/* Always place a cycle counter into the cycle counter. */
|
|
if (evtype == ARMV7_PERFCTR_CPU_CYCLES) {
|
|
if (test_and_set_bit(ARMV7_IDX_CYCLE_COUNTER, cpuc->used_mask))
|
|
return -EAGAIN;
|
|
|
|
return ARMV7_IDX_CYCLE_COUNTER;
|
|
}
|
|
|
|
/*
|
|
* For anything other than a cycle counter, try and use
|
|
* the events counters
|
|
*/
|
|
for (idx = ARMV7_IDX_COUNTER0; idx < cpu_pmu->num_events; ++idx) {
|
|
if (!test_and_set_bit(idx, cpuc->used_mask))
|
|
return idx;
|
|
}
|
|
|
|
/* The counters are all in use. */
|
|
return -EAGAIN;
|
|
}
|
|
|
|
/*
|
|
* Add an event filter to a given event. This will only work for PMUv2 PMUs.
|
|
*/
|
|
static int armv7pmu_set_event_filter(struct hw_perf_event *event,
|
|
struct perf_event_attr *attr)
|
|
{
|
|
unsigned long config_base = 0;
|
|
|
|
if (attr->exclude_idle)
|
|
return -EPERM;
|
|
if (attr->exclude_user)
|
|
config_base |= ARMV7_EXCLUDE_USER;
|
|
if (attr->exclude_kernel)
|
|
config_base |= ARMV7_EXCLUDE_PL1;
|
|
if (!attr->exclude_hv)
|
|
config_base |= ARMV7_INCLUDE_HYP;
|
|
|
|
/*
|
|
* Install the filter into config_base as this is used to
|
|
* construct the event type.
|
|
*/
|
|
event->config_base = config_base;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void armv7pmu_reset(void *info)
|
|
{
|
|
u32 idx, nb_cnt = cpu_pmu->num_events;
|
|
|
|
/* The counter and interrupt enable registers are unknown at reset. */
|
|
for (idx = ARMV7_IDX_CYCLE_COUNTER; idx < nb_cnt; ++idx)
|
|
armv7pmu_disable_event(NULL, idx);
|
|
|
|
/* Initialize & Reset PMNC: C and P bits */
|
|
armv7_pmnc_write(ARMV7_PMNC_P | ARMV7_PMNC_C);
|
|
}
|
|
|
|
static int armv7_a8_map_event(struct perf_event *event)
|
|
{
|
|
return map_cpu_event(event, &armv7_a8_perf_map,
|
|
&armv7_a8_perf_cache_map, 0xFF);
|
|
}
|
|
|
|
static int armv7_a9_map_event(struct perf_event *event)
|
|
{
|
|
return map_cpu_event(event, &armv7_a9_perf_map,
|
|
&armv7_a9_perf_cache_map, 0xFF);
|
|
}
|
|
|
|
static int armv7_a5_map_event(struct perf_event *event)
|
|
{
|
|
return map_cpu_event(event, &armv7_a5_perf_map,
|
|
&armv7_a5_perf_cache_map, 0xFF);
|
|
}
|
|
|
|
static int armv7_a15_map_event(struct perf_event *event)
|
|
{
|
|
return map_cpu_event(event, &armv7_a15_perf_map,
|
|
&armv7_a15_perf_cache_map, 0xFF);
|
|
}
|
|
|
|
static struct arm_pmu armv7pmu = {
|
|
.handle_irq = armv7pmu_handle_irq,
|
|
.enable = armv7pmu_enable_event,
|
|
.disable = armv7pmu_disable_event,
|
|
.read_counter = armv7pmu_read_counter,
|
|
.write_counter = armv7pmu_write_counter,
|
|
.get_event_idx = armv7pmu_get_event_idx,
|
|
.start = armv7pmu_start,
|
|
.stop = armv7pmu_stop,
|
|
.reset = armv7pmu_reset,
|
|
.max_period = (1LLU << 32) - 1,
|
|
};
|
|
|
|
static u32 __init armv7_read_num_pmnc_events(void)
|
|
{
|
|
u32 nb_cnt;
|
|
|
|
/* Read the nb of CNTx counters supported from PMNC */
|
|
nb_cnt = (armv7_pmnc_read() >> ARMV7_PMNC_N_SHIFT) & ARMV7_PMNC_N_MASK;
|
|
|
|
/* Add the CPU cycles counter and return */
|
|
return nb_cnt + 1;
|
|
}
|
|
|
|
static struct arm_pmu *__init armv7_a8_pmu_init(void)
|
|
{
|
|
armv7pmu.id = ARM_PERF_PMU_ID_CA8;
|
|
armv7pmu.name = "ARMv7 Cortex-A8";
|
|
armv7pmu.map_event = armv7_a8_map_event;
|
|
armv7pmu.num_events = armv7_read_num_pmnc_events();
|
|
return &armv7pmu;
|
|
}
|
|
|
|
static struct arm_pmu *__init armv7_a9_pmu_init(void)
|
|
{
|
|
armv7pmu.id = ARM_PERF_PMU_ID_CA9;
|
|
armv7pmu.name = "ARMv7 Cortex-A9";
|
|
armv7pmu.map_event = armv7_a9_map_event;
|
|
armv7pmu.num_events = armv7_read_num_pmnc_events();
|
|
return &armv7pmu;
|
|
}
|
|
|
|
static struct arm_pmu *__init armv7_a5_pmu_init(void)
|
|
{
|
|
armv7pmu.id = ARM_PERF_PMU_ID_CA5;
|
|
armv7pmu.name = "ARMv7 Cortex-A5";
|
|
armv7pmu.map_event = armv7_a5_map_event;
|
|
armv7pmu.num_events = armv7_read_num_pmnc_events();
|
|
return &armv7pmu;
|
|
}
|
|
|
|
static struct arm_pmu *__init armv7_a15_pmu_init(void)
|
|
{
|
|
armv7pmu.id = ARM_PERF_PMU_ID_CA15;
|
|
armv7pmu.name = "ARMv7 Cortex-A15";
|
|
armv7pmu.map_event = armv7_a15_map_event;
|
|
armv7pmu.num_events = armv7_read_num_pmnc_events();
|
|
armv7pmu.set_event_filter = armv7pmu_set_event_filter;
|
|
return &armv7pmu;
|
|
}
|
|
#else
|
|
static struct arm_pmu *__init armv7_a8_pmu_init(void)
|
|
{
|
|
return NULL;
|
|
}
|
|
|
|
static struct arm_pmu *__init armv7_a9_pmu_init(void)
|
|
{
|
|
return NULL;
|
|
}
|
|
|
|
static struct arm_pmu *__init armv7_a5_pmu_init(void)
|
|
{
|
|
return NULL;
|
|
}
|
|
|
|
static struct arm_pmu *__init armv7_a15_pmu_init(void)
|
|
{
|
|
return NULL;
|
|
}
|
|
#endif /* CONFIG_CPU_V7 */
|