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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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7334b3e47a
Add driver for the Internal RMII PHY found in the Amlogic Meson GXL SoCs. This PHY seems to only implement some standard registers and need some workarounds to provide autoneg values from vendor registers. Some magic values are currently used to configure the PHY, and this a temporary setup until clarification about these registers names and registers fields are provided by Amlogic. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
82 lines
2.3 KiB
C
82 lines
2.3 KiB
C
/*
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* Amlogic Meson GXL Internal PHY Driver
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*
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* Copyright (C) 2015 Amlogic, Inc. All rights reserved.
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* Copyright (C) 2016 BayLibre, SAS. All rights reserved.
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/mii.h>
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#include <linux/ethtool.h>
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#include <linux/phy.h>
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#include <linux/netdevice.h>
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static int meson_gxl_config_init(struct phy_device *phydev)
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{
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/* Enable Analog and DSP register Bank access by */
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phy_write(phydev, 0x14, 0x0000);
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phy_write(phydev, 0x14, 0x0400);
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phy_write(phydev, 0x14, 0x0000);
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phy_write(phydev, 0x14, 0x0400);
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/* Write Analog register 23 */
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phy_write(phydev, 0x17, 0x8E0D);
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phy_write(phydev, 0x14, 0x4417);
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/* Enable fractional PLL */
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phy_write(phydev, 0x17, 0x0005);
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phy_write(phydev, 0x14, 0x5C1B);
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/* Program fraction FR_PLL_DIV1 */
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phy_write(phydev, 0x17, 0x029A);
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phy_write(phydev, 0x14, 0x5C1D);
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/* Program fraction FR_PLL_DIV1 */
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phy_write(phydev, 0x17, 0xAAAA);
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phy_write(phydev, 0x14, 0x5C1C);
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return 0;
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}
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static struct phy_driver meson_gxl_phy[] = {
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{
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.phy_id = 0x01814400,
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.phy_id_mask = 0xfffffff0,
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.name = "Meson GXL Internal PHY",
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.features = PHY_BASIC_FEATURES,
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.flags = PHY_IS_INTERNAL,
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.config_init = meson_gxl_config_init,
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.config_aneg = genphy_config_aneg,
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.aneg_done = genphy_aneg_done,
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.read_status = genphy_read_status,
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.suspend = genphy_suspend,
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.resume = genphy_resume,
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},
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};
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static struct mdio_device_id __maybe_unused meson_gxl_tbl[] = {
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{ 0x01814400, 0xfffffff0 },
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{ }
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};
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module_phy_driver(meson_gxl_phy);
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MODULE_DEVICE_TABLE(mdio, meson_gxl_tbl);
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MODULE_DESCRIPTION("Amlogic Meson GXL Internal PHY driver");
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MODULE_AUTHOR("Baoqi wang");
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MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
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MODULE_LICENSE("GPL");
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