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IPI driver for the Open Multi-Processor Interrupt Controller (ompic) as described in the Multi-core support section of the OpenRISC 1.2 architecture specification: https://github.com/openrisc/doc/raw/master/openrisc-arch-1.2-rev0.pdf Each OpenRISC core contains a full interrupt controller which is used in the SMP architecture for interrupt balancing. This IPI device, the ompic, is the only external device required for enabling SMP on OpenRISC. Pending ops are stored in a memory bit mask which can allow multiple pending operations to be set and serviced at a time. This is mostly borrowed from the alpha IPI implementation. Reviewed-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi> [shorne@gmail.com: converted ops to bitmask, wrote commit message] Signed-off-by: Stafford Horne <shorne@gmail.com>
23 lines
723 B
Plaintext
23 lines
723 B
Plaintext
Open Multi-Processor Interrupt Controller
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Required properties:
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- compatible : This should be "openrisc,ompic"
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- reg : Specifies base physical address and size of the register space. The
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size is based on the number of cores the controller has been configured
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to handle, this should be set to 8 bytes per cpu core.
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- interrupt-controller : Identifies the node as an interrupt controller.
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- #interrupt-cells : This should be set to 0 as this will not be an irq
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parent.
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- interrupts : Specifies the interrupt line to which the ompic is wired.
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Example:
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ompic: interrupt-controller@98000000 {
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compatible = "openrisc,ompic";
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reg = <0x98000000 16>;
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interrupt-controller;
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#interrupt-cells = <0>;
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interrupts = <1>;
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};
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