mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-24 03:59:07 +07:00
5d8a00eee2
to existing clk drivers. The bulk of the work is on Allwinner and Rockchip SoCs, but there's also an Intel Atom driver in here too. New Drivers: - Tegra BPMP firmware - Hisilicon hi3660 SoCs - Rockchip rk3328 SoCs - Intel Atom PMC - STM32F746 - IDT VersaClock 5P49V5923 and 5P49V5933 - Marvell mv98dx3236 SoCs - Allwinner V3s SoCs Removed Drivers: - Samsung Exynos4415 SoCs Updates: - Migrate ABx500 to OF - Qualcomm IPQ4019 CPU clks and general PLL support - Qualcomm MSM8974 RPM - Rockchip non-critical fixes and clk id additions - Samsung Exynos4412 CPUs - Socionext UniPhier NAND and eMMC support - ZTE zx296718 i2s and other audio clks - Renesas CAN and MSIOF clks for R-Car M3-W - Renesas resets for R-Car Gen2 and Gen3 and RZ/G1 - TI CDCE913, CDCE937, and CDCE949 clk generators - Marvell Armada ap806 CPU frequencies - STM32F4* I2S/SAI support - Broadcom BCM2835 DSI support - Allwinner sun5i and A80 conversion to new style clk bindings -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.22 (GNU/Linux) iQIcBAABCAAGBQJYsLxxAAoJEK0CiJfG5JUl0p0P/AiBaYvrmHBx3H9jdC3iQxd2 7luFN3OqpykmZc3xx2xO3WaZ96kwwxiMu8sj3+VQo6oCkEuOY2ru6uPiDOcF4P3+ 8ku2taoWlESDbVLebVTNJoRXBaBLaV+9BCN7AKvXpVw+/UkJI5hgr0yMdh4tgtvu K08tTMkDNDbA33KXuJo8/chQFqi2W6XBXk22YMkqqA8jx0F4EM759LcgUlD1YfBS HKkgSOgsW3Zwhl27ZEAJMthcmS4+wFaEgFBeipg/hxTLI3aQtmDtRfXwg0wkbBx2 8sVz9SyBwkjOT9+41kve+Je94NK3blnJEjbxPASveMwyhdX1TlDQCPfrXya/1zxz N1By1NpA6iEYwi4hy+OtBYlcsBHztAM/+eljDY2kEDvfiKjMa44GYmgBu4n8pq+n 75NJxws6ZkzPs5/QsLT3hvTaL1SNX6PaEW8HabDXO40ccZc4CYvFZVOXMAnKaXzZ 31hj8EvQ5x6hci+SPYyVu6j3ipOxN96VcZqEJ+hWyyuZEMK6Up1o/0lGZFgwa0UD SIl7RiTFKO6ko+8hYlk1g0DGtEyWDsdso1Bw4zaHwMngM/CwjJVzpK5T2t1fJyEh lN5MdhcOi0nsiRWdRxOwOlHDLf93qSo87mvseU1MCEXYN1aqTV3VxSm1YU8ZgQVk sAjpsJqj45enfDa9BmIt =o8o/ -----END PGP SIGNATURE----- Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "The usual collection of new drivers, non-critical fixes, and updates to existing clk drivers. The bulk of the work is on Allwinner and Rockchip SoCs, but there's also an Intel Atom driver in here too. New Drivers: - Tegra BPMP firmware - Hisilicon hi3660 SoCs - Rockchip rk3328 SoCs - Intel Atom PMC - STM32F746 - IDT VersaClock 5P49V5923 and 5P49V5933 - Marvell mv98dx3236 SoCs - Allwinner V3s SoCs Removed Drivers: - Samsung Exynos4415 SoCs Updates: - Migrate ABx500 to OF - Qualcomm IPQ4019 CPU clks and general PLL support - Qualcomm MSM8974 RPM - Rockchip non-critical fixes and clk id additions - Samsung Exynos4412 CPUs - Socionext UniPhier NAND and eMMC support - ZTE zx296718 i2s and other audio clks - Renesas CAN and MSIOF clks for R-Car M3-W - Renesas resets for R-Car Gen2 and Gen3 and RZ/G1 - TI CDCE913, CDCE937, and CDCE949 clk generators - Marvell Armada ap806 CPU frequencies - STM32F4* I2S/SAI support - Broadcom BCM2835 DSI support - Allwinner sun5i and A80 conversion to new style clk bindings" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (130 commits) clk: renesas: mstp: ensure register writes complete clk: qcom: Do not drop device node twice clk: mvebu: adjust clock handling for the CP110 system controller clk: mvebu: Expand mv98dx3236-core-clock support clk: zte: add i2s clocks for zx296718 clk: sunxi-ng: sun9i-a80: Fix wrong pointer passed to PTR_ERR() clk: sunxi-ng: select SUNXI_CCU_MULT for sun5i clk: sunxi-ng: Check kzalloc() for errors and cleanup error path clk: tegra: Add BPMP clock driver clk: uniphier: add eMMC clock for LD11 and LD20 SoCs clk: uniphier: add NAND clock for all UniPhier SoCs ARM: dts: sun9i: Switch to new clock bindings clk: sunxi-ng: Add A80 Display Engine CCU clk: sunxi-ng: Add A80 USB CCU clk: sunxi-ng: Add A80 CCU clk: sunxi-ng: Support separately grouped PLL lock status register clk: sunxi-ng: mux: Get closest parent rate possible with CLK_SET_RATE_PARENT clk: sunxi-ng: mux: honor CLK_SET_RATE_NO_REPARENT flag clk: sunxi-ng: mux: Fix determine_rate for mux clocks with pre-dividers clk: qcom: SDHCI enablement on Nexus 5X / 6P ...
687 lines
16 KiB
Plaintext
687 lines
16 KiB
Plaintext
/*
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* Copyright 2016 Mylène Josserand
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*
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* Mylène Josserand <mylene.josserand@free-electrons.com>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <dt-bindings/clock/sun5i-ccu.h>
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#include <dt-bindings/dma/sun4i-a10.h>
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#include <dt-bindings/pinctrl/sun4i-a10.h>
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#include <dt-bindings/reset/sun5i-ccu.h>
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/ {
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interrupt-parent = <&intc>;
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a8";
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reg = <0x0>;
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clocks = <&ccu CLK_CPU>;
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};
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};
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clocks {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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osc24M: clk@01c20050 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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clock-output-names = "osc24M";
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};
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osc32k: clk@0 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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clock-output-names = "osc32k";
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};
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};
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display-engine {
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compatible = "allwinner,sun5i-a13-display-engine";
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allwinner,pipelines = <&fe0>;
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};
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soc@01c00000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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sram-controller@01c00000 {
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compatible = "allwinner,sun4i-a10-sram-controller";
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reg = <0x01c00000 0x30>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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sram_a: sram@00000000 {
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compatible = "mmio-sram";
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reg = <0x00000000 0xc000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x00000000 0xc000>;
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};
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sram_d: sram@00010000 {
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compatible = "mmio-sram";
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reg = <0x00010000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x00010000 0x1000>;
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otg_sram: sram-section@0000 {
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compatible = "allwinner,sun4i-a10-sram-d";
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reg = <0x0000 0x1000>;
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status = "disabled";
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};
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};
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};
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dma: dma-controller@01c02000 {
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compatible = "allwinner,sun4i-a10-dma";
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reg = <0x01c02000 0x1000>;
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interrupts = <27>;
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clocks = <&ccu CLK_AHB_DMA>;
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#dma-cells = <2>;
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};
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nfc: nand@01c03000 {
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compatible = "allwinner,sun4i-a10-nand";
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reg = <0x01c03000 0x1000>;
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interrupts = <37>;
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clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>;
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clock-names = "ahb", "mod";
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dmas = <&dma SUN4I_DMA_DEDICATED 3>;
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dma-names = "rxtx";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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spi0: spi@01c05000 {
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compatible = "allwinner,sun4i-a10-spi";
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reg = <0x01c05000 0x1000>;
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interrupts = <10>;
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clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>;
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clock-names = "ahb", "mod";
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dmas = <&dma SUN4I_DMA_DEDICATED 27>,
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<&dma SUN4I_DMA_DEDICATED 26>;
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dma-names = "rx", "tx";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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spi1: spi@01c06000 {
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compatible = "allwinner,sun4i-a10-spi";
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reg = <0x01c06000 0x1000>;
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interrupts = <11>;
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clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>;
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clock-names = "ahb", "mod";
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dmas = <&dma SUN4I_DMA_DEDICATED 9>,
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<&dma SUN4I_DMA_DEDICATED 8>;
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dma-names = "rx", "tx";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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tve0: tv-encoder@01c0a000 {
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compatible = "allwinner,sun4i-a10-tv-encoder";
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reg = <0x01c0a000 0x1000>;
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clocks = <&ccu CLK_AHB_TVE>;
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resets = <&ccu RST_TVE>;
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status = "disabled";
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port {
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#address-cells = <1>;
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#size-cells = <0>;
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tve0_in_tcon0: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&tcon0_out_tve0>;
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};
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};
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};
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tcon0: lcd-controller@01c0c000 {
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compatible = "allwinner,sun5i-a13-tcon";
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reg = <0x01c0c000 0x1000>;
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interrupts = <44>;
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resets = <&ccu RST_LCD>;
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reset-names = "lcd";
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clocks = <&ccu CLK_AHB_LCD>,
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<&ccu CLK_TCON_CH0>,
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<&ccu CLK_TCON_CH1>;
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clock-names = "ahb",
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"tcon-ch0",
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"tcon-ch1";
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clock-output-names = "tcon-pixel-clock";
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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tcon0_in: port@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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tcon0_in_be0: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&be0_out_tcon0>;
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};
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};
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tcon0_out: port@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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tcon0_out_tve0: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&tve0_in_tcon0>;
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};
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};
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};
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};
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mmc0: mmc@01c0f000 {
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compatible = "allwinner,sun5i-a13-mmc";
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reg = <0x01c0f000 0x1000>;
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clocks = <&ccu CLK_AHB_MMC0>, <&ccu CLK_MMC0>;
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clock-names = "ahb", "mmc";
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interrupts = <32>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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mmc1: mmc@01c10000 {
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compatible = "allwinner,sun5i-a13-mmc";
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reg = <0x01c10000 0x1000>;
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clocks = <&ccu CLK_AHB_MMC1>, <&ccu CLK_MMC1>;
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clock-names = "ahb", "mmc";
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interrupts = <33>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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mmc2: mmc@01c11000 {
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compatible = "allwinner,sun5i-a13-mmc";
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reg = <0x01c11000 0x1000>;
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clocks = <&ccu CLK_AHB_MMC2>, <&ccu CLK_MMC2>;
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clock-names = "ahb", "mmc";
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interrupts = <34>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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usb_otg: usb@01c13000 {
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compatible = "allwinner,sun4i-a10-musb";
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reg = <0x01c13000 0x0400>;
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clocks = <&ccu CLK_AHB_OTG>;
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interrupts = <38>;
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interrupt-names = "mc";
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phys = <&usbphy 0>;
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phy-names = "usb";
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extcon = <&usbphy 0>;
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allwinner,sram = <&otg_sram 1>;
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status = "disabled";
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dr_mode = "otg";
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};
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usbphy: phy@01c13400 {
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#phy-cells = <1>;
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compatible = "allwinner,sun5i-a13-usb-phy";
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reg = <0x01c13400 0x10 0x01c14800 0x4>;
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reg-names = "phy_ctrl", "pmu1";
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clocks = <&ccu CLK_USB_PHY0>;
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clock-names = "usb_phy";
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resets = <&ccu RST_USB_PHY0>, <&ccu RST_USB_PHY1>;
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reset-names = "usb0_reset", "usb1_reset";
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status = "disabled";
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};
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ehci0: usb@01c14000 {
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compatible = "allwinner,sun5i-a13-ehci", "generic-ehci";
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reg = <0x01c14000 0x100>;
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interrupts = <39>;
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clocks = <&ccu CLK_AHB_EHCI>;
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phys = <&usbphy 1>;
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phy-names = "usb";
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status = "disabled";
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};
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ohci0: usb@01c14400 {
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compatible = "allwinner,sun5i-a13-ohci", "generic-ohci";
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reg = <0x01c14400 0x100>;
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interrupts = <40>;
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clocks = <&ccu CLK_USB_OHCI>, <&ccu CLK_AHB_OHCI>;
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phys = <&usbphy 1>;
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phy-names = "usb";
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status = "disabled";
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};
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spi2: spi@01c17000 {
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compatible = "allwinner,sun4i-a10-spi";
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reg = <0x01c17000 0x1000>;
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interrupts = <12>;
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clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>;
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clock-names = "ahb", "mod";
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dmas = <&dma SUN4I_DMA_DEDICATED 29>,
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<&dma SUN4I_DMA_DEDICATED 28>;
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dma-names = "rx", "tx";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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ccu: clock@01c20000 {
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compatible = "nextthing,gr8-ccu";
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reg = <0x01c20000 0x400>;
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clocks = <&osc24M>, <&osc32k>;
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clock-names = "hosc", "losc";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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intc: interrupt-controller@01c20400 {
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compatible = "allwinner,sun4i-a10-ic";
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reg = <0x01c20400 0x400>;
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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pio: pinctrl@01c20800 {
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compatible = "nextthing,gr8-pinctrl";
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reg = <0x01c20800 0x400>;
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interrupts = <28>;
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clocks = <&ccu CLK_APB0_PIO>;
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gpio-controller;
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interrupt-controller;
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#interrupt-cells = <3>;
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#gpio-cells = <3>;
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i2c0_pins_a: i2c0@0 {
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pins = "PB0", "PB1";
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function = "i2c0";
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};
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i2c1_pins_a: i2c1@0 {
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pins = "PB15", "PB16";
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function = "i2c1";
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};
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i2c2_pins_a: i2c2@0 {
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pins = "PB17", "PB18";
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function = "i2c2";
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};
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i2s0_data_pins_a: i2s0-data@0 {
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pins = "PB6", "PB7", "PB8", "PB9";
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function = "i2s0";
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};
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i2s0_mclk_pins_a: i2s0-mclk@0 {
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pins = "PB5";
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function = "i2s0";
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};
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ir0_rx_pins_a: ir0@0 {
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pins = "PB4";
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function = "ir0";
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};
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lcd_rgb666_pins: lcd-rgb666@0 {
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pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
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"PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
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"PD18", "PD19", "PD20", "PD21", "PD22", "PD23",
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"PD24", "PD25", "PD26", "PD27";
|
|
function = "lcd0";
|
|
};
|
|
|
|
mmc0_pins_a: mmc0@0 {
|
|
pins = "PF0", "PF1", "PF2", "PF3",
|
|
"PF4", "PF5";
|
|
function = "mmc0";
|
|
drive-strength = <30>;
|
|
};
|
|
|
|
nand_pins_a: nand-base0@0 {
|
|
pins = "PC0", "PC1", "PC2",
|
|
"PC5", "PC8", "PC9", "PC10",
|
|
"PC11", "PC12", "PC13", "PC14",
|
|
"PC15";
|
|
function = "nand0";
|
|
};
|
|
|
|
nand_cs0_pins_a: nand-cs@0 {
|
|
pins = "PC4";
|
|
function = "nand0";
|
|
};
|
|
|
|
nand_rb0_pins_a: nand-rb@0 {
|
|
pins = "PC6";
|
|
function = "nand0";
|
|
};
|
|
|
|
pwm0_pins_a: pwm0@0 {
|
|
pins = "PB2";
|
|
function = "pwm0";
|
|
};
|
|
|
|
pwm1_pins: pwm1 {
|
|
pins = "PG13";
|
|
function = "pwm1";
|
|
};
|
|
|
|
spdif_tx_pins_a: spdif@0 {
|
|
pins = "PB10";
|
|
function = "spdif";
|
|
bias-pull-up;
|
|
};
|
|
|
|
uart1_pins_a: uart1@1 {
|
|
pins = "PG3", "PG4";
|
|
function = "uart1";
|
|
};
|
|
|
|
uart1_cts_rts_pins_a: uart1-cts-rts@0 {
|
|
pins = "PG5", "PG6";
|
|
function = "uart1";
|
|
};
|
|
|
|
uart2_pins_a: uart2@1 {
|
|
pins = "PD2", "PD3";
|
|
function = "uart2";
|
|
};
|
|
|
|
uart2_cts_rts_pins_a: uart2-cts-rts@0 {
|
|
pins = "PD4", "PD5";
|
|
function = "uart2";
|
|
};
|
|
|
|
uart3_pins_a: uart3@1 {
|
|
pins = "PG9", "PG10";
|
|
function = "uart3";
|
|
};
|
|
|
|
uart3_cts_rts_pins_a: uart3-cts-rts@0 {
|
|
pins = "PG11", "PG12";
|
|
function = "uart3";
|
|
};
|
|
};
|
|
|
|
pwm: pwm@01c20e00 {
|
|
compatible = "allwinner,sun5i-a10s-pwm";
|
|
reg = <0x01c20e00 0xc>;
|
|
clocks = <&ccu CLK_HOSC>;
|
|
#pwm-cells = <3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
timer@01c20c00 {
|
|
compatible = "allwinner,sun4i-a10-timer";
|
|
reg = <0x01c20c00 0x90>;
|
|
interrupts = <22>;
|
|
clocks = <&ccu CLK_HOSC>;
|
|
};
|
|
|
|
wdt: watchdog@01c20c90 {
|
|
compatible = "allwinner,sun4i-a10-wdt";
|
|
reg = <0x01c20c90 0x10>;
|
|
};
|
|
|
|
spdif: spdif@01c21000 {
|
|
#sound-dai-cells = <0>;
|
|
compatible = "allwinner,sun4i-a10-spdif";
|
|
reg = <0x01c21000 0x400>;
|
|
interrupts = <13>;
|
|
clocks = <&ccu CLK_APB0_SPDIF>, <&ccu CLK_SPDIF>;
|
|
clock-names = "apb", "spdif";
|
|
dmas = <&dma SUN4I_DMA_NORMAL 2>,
|
|
<&dma SUN4I_DMA_NORMAL 2>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
ir0: ir@01c21800 {
|
|
compatible = "allwinner,sun4i-a10-ir";
|
|
clocks = <&ccu CLK_APB0_IR>, <&ccu CLK_IR>;
|
|
clock-names = "apb", "ir";
|
|
interrupts = <5>;
|
|
reg = <0x01c21800 0x40>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2s0: i2s@01c22400 {
|
|
#sound-dai-cells = <0>;
|
|
compatible = "allwinner,sun4i-a10-i2s";
|
|
reg = <0x01c22400 0x400>;
|
|
interrupts = <16>;
|
|
clocks = <&ccu CLK_APB0_I2S>, <&ccu CLK_I2S>;
|
|
clock-names = "apb", "mod";
|
|
dmas = <&dma SUN4I_DMA_NORMAL 3>,
|
|
<&dma SUN4I_DMA_NORMAL 3>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
lradc: lradc@01c22800 {
|
|
compatible = "allwinner,sun4i-a10-lradc-keys";
|
|
reg = <0x01c22800 0x100>;
|
|
interrupts = <31>;
|
|
status = "disabled";
|
|
};
|
|
|
|
codec: codec@01c22c00 {
|
|
#sound-dai-cells = <0>;
|
|
compatible = "allwinner,sun4i-a10-codec";
|
|
reg = <0x01c22c00 0x40>;
|
|
interrupts = <30>;
|
|
clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>;
|
|
clock-names = "apb", "codec";
|
|
dmas = <&dma SUN4I_DMA_NORMAL 19>,
|
|
<&dma SUN4I_DMA_NORMAL 19>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
rtp: rtp@01c25000 {
|
|
compatible = "allwinner,sun5i-a13-ts";
|
|
reg = <0x01c25000 0x100>;
|
|
interrupts = <29>;
|
|
#thermal-sensor-cells = <0>;
|
|
};
|
|
|
|
uart1: serial@01c28400 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x01c28400 0x400>;
|
|
interrupts = <2>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&ccu CLK_APB1_UART1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart2: serial@01c28800 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x01c28800 0x400>;
|
|
interrupts = <3>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&ccu CLK_APB1_UART2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart3: serial@01c28c00 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x01c28c00 0x400>;
|
|
interrupts = <4>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&ccu CLK_APB1_UART3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c0: i2c@01c2ac00 {
|
|
compatible = "allwinner,sun4i-a10-i2c";
|
|
reg = <0x01c2ac00 0x400>;
|
|
interrupts = <7>;
|
|
clocks = <&ccu CLK_APB1_I2C0>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
i2c1: i2c@01c2b000 {
|
|
compatible = "allwinner,sun4i-a10-i2c";
|
|
reg = <0x01c2b000 0x400>;
|
|
interrupts = <8>;
|
|
clocks = <&ccu CLK_APB1_I2C1>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
i2c2: i2c@01c2b400 {
|
|
compatible = "allwinner,sun4i-a10-i2c";
|
|
reg = <0x01c2b400 0x400>;
|
|
interrupts = <9>;
|
|
clocks = <&ccu CLK_APB1_I2C2>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
timer@01c60000 {
|
|
compatible = "allwinner,sun5i-a13-hstimer";
|
|
reg = <0x01c60000 0x1000>;
|
|
interrupts = <82>, <83>;
|
|
clocks = <&ccu CLK_AHB_HSTIMER>;
|
|
};
|
|
|
|
fe0: display-frontend@01e00000 {
|
|
compatible = "allwinner,sun5i-a13-display-frontend";
|
|
reg = <0x01e00000 0x20000>;
|
|
interrupts = <47>;
|
|
clocks = <&ccu CLK_AHB_DE_FE>, <&ccu CLK_DE_FE>,
|
|
<&ccu CLK_DRAM_DE_FE>;
|
|
clock-names = "ahb", "mod",
|
|
"ram";
|
|
resets = <&ccu RST_DE_FE>;
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
fe0_out: port@1 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <1>;
|
|
|
|
fe0_out_be0: endpoint@0 {
|
|
reg = <0>;
|
|
remote-endpoint = <&be0_in_fe0>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
be0: display-backend@01e60000 {
|
|
compatible = "allwinner,sun5i-a13-display-backend";
|
|
reg = <0x01e60000 0x10000>;
|
|
clocks = <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
|
|
<&ccu CLK_DRAM_DE_BE>;
|
|
clock-names = "ahb", "mod",
|
|
"ram";
|
|
resets = <&ccu RST_DE_BE>;
|
|
status = "disabled";
|
|
|
|
assigned-clocks = <&ccu CLK_DE_BE>;
|
|
assigned-clock-rates = <300000000>;
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
be0_in: port@0 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0>;
|
|
|
|
be0_in_fe0: endpoint@0 {
|
|
reg = <0>;
|
|
remote-endpoint = <&fe0_out_be0>;
|
|
};
|
|
};
|
|
|
|
be0_out: port@1 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <1>;
|
|
|
|
be0_out_tcon0: endpoint@0 {
|
|
reg = <0>;
|
|
remote-endpoint = <&tcon0_in_be0>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
};
|
|
};
|